spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()

[oweals/u-boot.git] / arch / arm / mach-stm32mp / cpu.c

diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 9c5e0448ce5a94dd485190189d909b13010a1e8b..74d03fa7dd82fff41a0f1318fe2b109f6b77851e 100644 (file)
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -76,7 +76,7 @@
 #define PKG_MASK       GENMASK(2, 0)
 
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-#ifndef CONFIG_STM32MP1_TRUSTED
+#ifndef CONFIG_TFABOOT
 static void security_init(void)
 {
        /* Disable the backup domain write protection */
@@ -136,7 +136,7 @@ static void security_init(void)
        writel(BIT(0), RCC_MP_AHB5ENSETR);
        writel(0x0, GPIOZ_SECCFGR);
 }
-#endif /* CONFIG_STM32MP1_TRUSTED */
+#endif /* CONFIG_TFABOOT */
 
 /*
  * Debug init
@@ -150,7 +150,7 @@ static void dbgmcu_init(void)
 }
 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
 
-#if !defined(CONFIG_STM32MP1_TRUSTED) && \
+#if !defined(CONFIG_TFABOOT) && \
        (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 /* get bootmode from ROM code boot context: saved in TAMP register */
 static void update_bootmode(void)
@@ -198,7 +198,7 @@ int arch_cpu_init(void)
 
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
        dbgmcu_init();
-#ifndef CONFIG_STM32MP1_TRUSTED
+#ifndef CONFIG_TFABOOT
        security_init();
        update_bootmode();
 #endif
@@ -214,7 +214,7 @@ int arch_cpu_init(void)
        if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
                gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
 #if defined(CONFIG_DEBUG_UART) && \
-       !defined(CONFIG_STM32MP1_TRUSTED) && \
+       !defined(CONFIG_TFABOOT) && \
        (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
        else
                debug_uart_init();
@@ -285,18 +285,36 @@ void get_soc_name(char name[SOC_NAME_SIZE])
 
        /* MPUs Part Numbers */
        switch (get_cpu_type()) {
+       case CPU_STM32MP157Fxx:
+               cpu_s = "157F";
+               break;
+       case CPU_STM32MP157Dxx:
+               cpu_s = "157D";
+               break;
        case CPU_STM32MP157Cxx:
                cpu_s = "157C";
                break;
        case CPU_STM32MP157Axx:
                cpu_s = "157A";
                break;
+       case CPU_STM32MP153Fxx:
+               cpu_s = "153F";
+               break;
+       case CPU_STM32MP153Dxx:
+               cpu_s = "153D";
+               break;
        case CPU_STM32MP153Cxx:
                cpu_s = "153C";
                break;
        case CPU_STM32MP153Axx:
                cpu_s = "153A";
                break;
+       case CPU_STM32MP151Fxx:
+               cpu_s = "151F";
+               break;
+       case CPU_STM32MP151Dxx:
+               cpu_s = "151D";
+               break;
        case CPU_STM32MP151Cxx:
                cpu_s = "151C";
                break;