arm: socfpga: Convert reset manager from struct to defines

[oweals/u-boot.git] / arch / arm / mach-socfpga / spl_gen5.c

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 9dd0afb4bcacd905e2287a52acdd011d09182b26..bbaa5d3d323bb56c36b5a3568c0a48004ee3754e 100644 (file)
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -5,7 +5,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -25,8 +24,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
-       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static const struct socfpga_system_manager *sysmgr_regs =
        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -63,60 +60,6 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-static void socfpga_pl310_clear(void)
-{
-       u32 mask = 0xff, ena = 0;
-
-       icache_enable();
-
-       /* Disable the L2 cache */
-       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
-       writel(0x111, &pl310->pl310_tag_latency_ctrl);
-       writel(0x121, &pl310->pl310_data_latency_ctrl);
-
-       /* enable BRESP, instruction and data prefetch, full line of zeroes */
-       setbits_le32(&pl310->pl310_aux_ctrl,
-                    L310_AUX_CTRL_DATA_PREFETCH_MASK |
-                    L310_AUX_CTRL_INST_PREFETCH_MASK |
-                    L310_SHARED_ATT_OVERRIDE_ENABLE);
-
-       /* Enable the L2 cache */
-       ena = readl(&pl310->pl310_ctrl);
-       ena |= L2X0_CTRL_EN;
-
-       /*
-        * Invalidate the PL310 L2 cache. Keep the invalidation code
-        * entirely in L1 I-cache to avoid any bus traffic through
-        * the L2.
-        */
-       asm volatile(
-               ".align 5                       \n"
-               "       b       3f              \n"
-               "1:     str     %1,     [%4]    \n"
-               "       dsb                     \n"
-               "       isb                     \n"
-               "       str     %0,     [%2]    \n"
-               "       dsb                     \n"
-               "       isb                     \n"
-               "2:     ldr     %0,     [%2]    \n"
-               "       cmp     %0,     #0      \n"
-               "       bne     2b              \n"
-               "       str     %0,     [%3]    \n"
-               "       dsb                     \n"
-               "       isb                     \n"
-               "       b       4f              \n"
-               "3:     b       1b              \n"
-               "4:     nop                     \n"
-       : "+r"(mask), "+r"(ena)
-       : "r"(&pl310->pl310_inv_way),
-         "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
-       : "memory", "cc");
-
-       /* Disable the L2 cache */
-       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
 void board_init_f(ulong dummy)
 {
        const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -124,8 +67,14 @@ void board_init_f(ulong dummy)
        int ret;
        struct udevice *dev;
 
+       ret = spl_early_init();
+       if (ret)
+               hang();
+
+       socfpga_get_managers_addr();
+
        /*
-        * First C code to run. Clear fake OCRAM ECC first as SBE
+        * Clear fake OCRAM ECC first as SBE
         * and DBE might triggered during power on
         */
        reg = readl(&sysmgr_regs->eccgrp_ocram);
@@ -136,8 +85,6 @@ void board_init_f(ulong dummy)
                writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
                       &sysmgr_regs->eccgrp_ocram);
 
-       memset(__bss_start, 0, __bss_end - __bss_start);
-
        socfpga_sdram_remap_zero();
        socfpga_pl310_clear();
 
@@ -175,8 +122,8 @@ void board_init_f(ulong dummy)
        sysmgr_pinmux_init();
        sysmgr_config_warmrstcfgio(0);
 
-       /* De-assert reset for bridges based on handoff */
-       socfpga_bridges_reset(0);
+       /* Set bridges handoff value */
+       socfpga_bridges_set_handoff_regs(true, true, true);
 
        debug("Unfreezing/Thaw all I/O banks\n");
        /* unfreeze / thaw all IO banks */
@@ -187,16 +134,17 @@ void board_init_f(ulong dummy)
        debug_uart_init();
 #endif
 
-       ret = spl_early_init();
-       if (ret) {
-               debug("spl_early_init() failed: %d\n", ret);
-               hang();
-       }
-
        ret = uclass_get_device(UCLASS_RESET, 0, &dev);
        if (ret)
                debug("Reset init failed: %d\n", ret);
 
+#ifdef CONFIG_SPL_NAND_DENALI
+       struct socfpga_reset_manager *reset_manager_base =
+               (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+
+       clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4));
+#endif
+
        /* enable console uart printing */
        preloader_console_init();
 
@@ -205,7 +153,4 @@ void board_init_f(ulong dummy)
                debug("DRAM init failed: %d\n", ret);
                hang();
        }
-
-       if (!socfpga_is_booting_from_fpga())
-               socfpga_bridges_reset(1);
 }