#include <asm/arch/misc.h>
#include <asm/arch/scan_manager.h>
#include <asm/arch/sdram.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/nic301.h>
#include <asm/sections.h>
#include <debug_uart.h>
#include <fdtdec.h>
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct scu_registers *scu_regs =
- (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct nic301_registers *nic301_regs =
- (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(const u32 boot_device)
{
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
}
#endif
-static void socfpga_nic301_slave_ns(void)
+static void socfpga_pl310_clear(void)
{
- writel(0x1, &nic301_regs->lwhps2fpgaregs);
- writel(0x1, &nic301_regs->hps2fpgaregs);
- writel(0x1, &nic301_regs->acp);
- writel(0x1, &nic301_regs->rom);
- writel(0x1, &nic301_regs->ocram);
- writel(0x1, &nic301_regs->sdrdata);
+ u32 mask = 0xff, ena = 0;
+
+ icache_enable();
+
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ writel(0x111, &pl310->pl310_tag_latency_ctrl);
+ writel(0x121, &pl310->pl310_data_latency_ctrl);
+
+ /* enable BRESP, instruction and data prefetch, full line of zeroes */
+ setbits_le32(&pl310->pl310_aux_ctrl,
+ L310_AUX_CTRL_DATA_PREFETCH_MASK |
+ L310_AUX_CTRL_INST_PREFETCH_MASK |
+ L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ ena = readl(&pl310->pl310_ctrl);
+ ena |= L2X0_CTRL_EN;
+
+ /*
+ * Invalidate the PL310 L2 cache. Keep the invalidation code
+ * entirely in L1 I-cache to avoid any bus traffic through
+ * the L2.
+ */
+ asm volatile(
+ ".align 5 \n"
+ " b 3f \n"
+ "1: str %1, [%4] \n"
+ " dsb \n"
+ " isb \n"
+ " str %0, [%2] \n"
+ " dsb \n"
+ " isb \n"
+ "2: ldr %0, [%2] \n"
+ " cmp %0, #0 \n"
+ " bne 2b \n"
+ " str %0, [%3] \n"
+ " dsb \n"
+ " isb \n"
+ " b 4f \n"
+ "3: b 1b \n"
+ "4: nop \n"
+ : "+r"(mask), "+r"(ena)
+ : "r"(&pl310->pl310_inv_way),
+ "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
+ : "memory", "cc");
+
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
void board_init_f(ulong dummy)
memset(__bss_start, 0, __bss_end - __bss_start);
- socfpga_nic301_slave_ns();
-
- /* Configure ARM MPU SNSAC register. */
- setbits_le32(&scu_regs->sacr, 0xfff);
-
- /* Remap SDRAM to 0x0 */
- writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
- writel(0x1, &pl310->pl310_addr_filter_start);
+ socfpga_sdram_remap_zero();
+ socfpga_pl310_clear();
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
/* Put everything into reset but L4WD0. */
socfpga_per_reset_all();
- /* Put FPGA bridges into reset too. */
- socfpga_bridges_reset(1);
+
+ if (!socfpga_is_booting_from_fpga()) {
+ /* Put FPGA bridges into reset too. */
+ socfpga_bridges_reset(1);
+ }
socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
hang();
}
- socfpga_bridges_reset(1);
+ if (!socfpga_is_booting_from_fpga())
+ socfpga_bridges_reset(1);
}