#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(const u32 boot_device)
{
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
void spl_board_init(void)
{
- /* configuring the clock based on handoff */
- cm_basic_init(gd->fdt_blob);
- WATCHDOG_RESET();
-
- config_dedicated_pins(gd->fdt_blob);
- WATCHDOG_RESET();
-
/* enable console uart printing */
preloader_console_init();
-
WATCHDOG_RESET();
- /* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
+ arch_early_init_r();
}
void board_init_f(ulong dummy)
{
- /*
- * Configure Clock Manager to use intosc clock instead external osc to
- * ensure success watchdog operation. We do it as early as possible.
- */
- cm_use_intosc();
+ dcache_disable();
+ socfpga_init_security_policies();
+ socfpga_sdram_remap_zero();
+
+ /* Assert reset to all except L4WD0 and L4TIMER0 */
+ socfpga_per_reset_all();
socfpga_watchdog_disable();
- arch_early_init_r();
+ spl_early_init();
+
+ /* Configure the clock based on handoff */
+ cm_basic_init(gd->fdt_blob);
#ifdef CONFIG_HW_WATCHDOG
/* release osc1 watchdog timer 0 from reset */
hw_watchdog_init();
WATCHDOG_RESET();
#endif /* CONFIG_HW_WATCHDOG */
+
+ config_dedicated_pins(gd->fdt_blob);
+ WATCHDOG_RESET();
}