Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-boot
[oweals/u-boot.git] / arch / arm / mach-socfpga / spl_a10.c
index 7d35e9daa828249554217f01323b08dfe653a0b0..c8e73d47c0b40c3ac11e42f5b07059b255448ba7 100644 (file)
@@ -58,7 +58,7 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 u32 spl_boot_mode(const u32 boot_device)
 {
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
        return MMCSD_MODE_FS;
 #else
        return MMCSD_MODE_RAW;
@@ -68,33 +68,28 @@ u32 spl_boot_mode(const u32 boot_device)
 
 void spl_board_init(void)
 {
-       /* configuring the clock based on handoff */
-       cm_basic_init(gd->fdt_blob);
-       WATCHDOG_RESET();
-
-       config_dedicated_pins(gd->fdt_blob);
-       WATCHDOG_RESET();
-
        /* enable console uart printing */
        preloader_console_init();
-
        WATCHDOG_RESET();
 
-       /* Add device descriptor to FPGA device table */
-       socfpga_fpga_add();
+       arch_early_init_r();
 }
 
 void board_init_f(ulong dummy)
 {
-       /*
-        * Configure Clock Manager to use intosc clock instead external osc to
-        * ensure success watchdog operation. We do it as early as possible.
-        */
-       cm_use_intosc();
+       dcache_disable();
 
+       socfpga_init_security_policies();
+       socfpga_sdram_remap_zero();
+
+       /* Assert reset to all except L4WD0 and L4TIMER0 */
+       socfpga_per_reset_all();
        socfpga_watchdog_disable();
 
-       arch_early_init_r();
+       spl_early_init();
+
+       /* Configure the clock based on handoff */
+       cm_basic_init(gd->fdt_blob);
 
 #ifdef CONFIG_HW_WATCHDOG
        /* release osc1 watchdog timer 0 from reset */
@@ -104,4 +99,7 @@ void board_init_f(ulong dummy)
        hw_watchdog_init();
        WATCHDOG_RESET();
 #endif /* CONFIG_HW_WATCHDOG */
+
+       config_dedicated_pins(gd->fdt_blob);
+       WATCHDOG_RESET();
 }