// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
*/
#include <common.h>
+#include <cpu_func.h>
#include <asm/io.h>
#include <asm/pl310.h>
#include <asm/u-boot.h>
#include <fdtdec.h>
#include <watchdog.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/fpga_manager.h>
+#include <mmc.h>
+#include <memalign.h>
+
+#define FPGA_BUFSIZ 16 * 1024
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
arch_early_init_r();
+
+ /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+ if (is_fpgamgr_user_mode()) {
+ int ret = config_pins(gd->fdt_blob, "shared");
+
+ if (ret)
+ return;
+
+ ret = config_pins(gd->fdt_blob, "fpga");
+ if (ret)
+ return;
+ } else if (!is_fpgamgr_early_user_mode()) {
+ /* Program IOSSM(early IO release) or full FPGA */
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+ }
+
+ /* If the IOSSM/full FPGA is already loaded, start DDR */
+ if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+ ddr_calibration_sequence();
+
+ if (!is_fpgamgr_user_mode())
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
}
void board_init_f(ulong dummy)
{
+ if (spl_early_init())
+ hang();
+
+ socfpga_get_managers_addr();
+
dcache_disable();
socfpga_init_security_policies();
socfpga_sdram_remap_zero();
+ socfpga_pl310_clear();
/* Assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
socfpga_watchdog_disable();
- spl_early_init();
-
/* Configure the clock based on handoff */
cm_basic_init(gd->fdt_blob);