arm: socfpga: Do not call board_init_r() from board_init_f()

[oweals/u-boot.git] / arch / arm / mach-socfpga / spl.c

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index f134bb794fc4b8faad5eccf888701d6041934e6d..775a82780f7fb9b2aac63d859f829ca08f2c125f 100644 (file)
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -28,6 +28,44 @@ static struct scu_registers *scu_regs =
        (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
        (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+       const u32 bsel = readl(&sysmgr_regs->bootinfo);
+
+       switch (bsel & 0x7) {
+       case 0x1:       /* FPGA (HPS2FPGA Bridge) */
+               return BOOT_DEVICE_RAM;
+       case 0x2:       /* NAND Flash (1.8V) */
+       case 0x3:       /* NAND Flash (3.0V) */
+               return BOOT_DEVICE_NAND;
+       case 0x4:       /* SD/MMC External Transceiver (1.8V) */
+       case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
+               socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+               socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+               return BOOT_DEVICE_MMC1;
+       case 0x6:       /* QSPI Flash (1.8V) */
+       case 0x7:       /* QSPI Flash (3.0V) */
+               socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+               return BOOT_DEVICE_SPI;
+       default:
+               printf("Invalid boot device (bsel=%08x)!\n", bsel);
+               hang();
+       }
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+       return MMCSD_MODE_FS;
+#else
+       return MMCSD_MODE_RAW;
+#endif
+}
+#endif
 
 static void socfpga_nic301_slave_ns(void)
 {
@@ -41,9 +79,12 @@ static void socfpga_nic301_slave_ns(void)
 
 void board_init_f(ulong dummy)
 {
-       struct socfpga_system_manager *sysmgr_regs =
-               (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+       const struct cm_config *cm_default_cfg = cm_get_default_config();
+#endif
+       unsigned long sdram_size;
        unsigned long reg;
+
        /*
         * First C code to run. Clear fake OCRAM ECC first as SBE
         * and DBE might triggered during power on
@@ -67,24 +108,7 @@ void board_init_f(ulong dummy)
        writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
        writel(0x1, &pl310->pl310_addr_filter_start);
 
-       board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
-{
-       return BOOT_DEVICE_RAM;
-}
-
-/*
- * Board initialization after bss clearance
- */
-void spl_board_init(void)
-{
-       unsigned long sdram_size;
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-       const struct cm_config *cm_default_cfg = cm_get_default_config();
-#endif
-
        debug("Freezing all I/O banks\n");
        /* freeze all IO banks */
        sys_mgr_frzctrl_freeze_req();
@@ -153,4 +177,7 @@ void spl_board_init(void)
        }
 
        socfpga_bridges_reset(1);
+
+       /* Configure simple malloc base pointer into RAM. */
+       gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }