ARM: socfpga: fix duplicate const specifier warning

[oweals/u-boot.git] / arch / arm / mach-socfpga / spl.c

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index ea0ed1a24d7fd18fbcc63658b52262f1f82f8508..71bae827a15b3b07df8594c82912da0db33d790b 100644 (file)
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -19,21 +19,65 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
        (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
        (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
        (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
+       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
-       return BOOT_DEVICE_RAM;
+       const u32 bsel = readl(&sysmgr_regs->bootinfo);
+
+       switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+       case 0x1:       /* FPGA (HPS2FPGA Bridge) */
+               return BOOT_DEVICE_RAM;
+       case 0x2:       /* NAND Flash (1.8V) */
+       case 0x3:       /* NAND Flash (3.0V) */
+               socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+               return BOOT_DEVICE_NAND;
+       case 0x4:       /* SD/MMC External Transceiver (1.8V) */
+       case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
+               socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+               socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+               return BOOT_DEVICE_MMC1;
+       case 0x6:       /* QSPI Flash (1.8V) */
+       case 0x7:       /* QSPI Flash (3.0V) */
+               socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+               return BOOT_DEVICE_SPI;
+       default:
+               printf("Invalid boot device (bsel=%08x)!\n", bsel);
+               hang();
+       }
 }
 
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+       return MMCSD_MODE_FS;
+#else
+       return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
        writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -49,8 +93,6 @@ void board_init_f(ulong dummy)
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
        const struct cm_config *cm_default_cfg = cm_get_default_config();
 #endif
-       struct socfpga_system_manager *sysmgr_regs =
-               (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
        unsigned long sdram_size;
        unsigned long reg;
 
@@ -95,7 +137,8 @@ void board_init_f(ulong dummy)
 
        debug("Reconfigure Clock Manager\n");
        /* reconfigure the PLLs */
-       cm_basic_init(cm_default_cfg);
+       if (cm_basic_init(cm_default_cfg))
+               hang();
 
        /* Enable bootrom to configure IOs. */
        sysmgr_config_warmrstcfgio(1);
@@ -147,5 +190,45 @@ void board_init_f(ulong dummy)
 
        socfpga_bridges_reset(1);
 
-       board_init_r(NULL, 0);
+       /* Configure simple malloc base pointer into RAM. */
+       gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void spl_board_init(void)
+{
+       /* configuring the clock based on handoff */
+       cm_basic_init(gd->fdt_blob);
+       WATCHDOG_RESET();
+
+       config_dedicated_pins(gd->fdt_blob);
+       WATCHDOG_RESET();
+
+       /* Release UART from reset */
+       socfpga_reset_uart(0);
+
+       /* enable console uart printing */
+       preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+       /*
+        * Configure Clock Manager to use intosc clock instead external osc to
+        * ensure success watchdog operation. We do it as early as possible.
+        */
+       cm_use_intosc();
+
+       socfpga_watchdog_disable();
+
+       arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+       /* release osc1 watchdog timer 0 from reset */
+       socfpga_reset_deassert_osc1wd0();
+
+       /* reconfigure and enable the watchdog */
+       hw_watchdog_init();
+       WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
+#endif