arm: socfpga: Convert reset manager from struct to defines

[oweals/u-boot.git] / arch / arm / mach-socfpga / reset_manager_s10.c

diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index f8dd787cc6ae41069222d96e1d7f362ba81b0501..8af28ee410c50d08615b360207425dfb6bcb0ec7 100644 (file)
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -12,31 +12,31 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_reset_manager *reset_manager_base =
-               (void *)SOCFPGA_RSTMGR_ADDRESS;
 static const struct socfpga_system_manager *system_manager_base =
                (void *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
 {
-       const void *reg;
+       unsigned long reg;
 
        if (RSTMGR_BANK(reset) == 0)
-               reg = &reset_manager_base->mpumodrst;
+               reg = RSTMGR_S10_MPUMODRST;
        else if (RSTMGR_BANK(reset) == 1)
-               reg = &reset_manager_base->per0modrst;
+               reg = RSTMGR_S10_PER0MODRST;
        else if (RSTMGR_BANK(reset) == 2)
-               reg = &reset_manager_base->per1modrst;
+               reg = RSTMGR_S10_PER1MODRST;
        else if (RSTMGR_BANK(reset) == 3)
-               reg = &reset_manager_base->brgmodrst;
+               reg = RSTMGR_S10_BRGMODRST;
        else    /* Invalid reset register, do nothing */
                return;
 
        if (set)
-               setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+               setbits_le32(socfpga_get_rstmgr_addr() + reg,
+                            1 << RSTMGR_RESET(reset));
        else
-               clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+               clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+                            1 << RSTMGR_RESET(reset));
 }
 
 /*
@@ -50,9 +50,9 @@ void socfpga_per_reset_all(void)
 
        /* disable all except OCP and l4wd0. OCP disable later */
        writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
-              &reset_manager_base->per0modrst);
-       writel(~l4wd0, &reset_manager_base->per0modrst);
-       writel(0xffffffff, &reset_manager_base->per1modrst);
+                     socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
+       writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
+       writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER1MODRST);
 }
 
 void socfpga_bridges_reset(int enable)
@@ -61,8 +61,9 @@ void socfpga_bridges_reset(int enable)
                /* clear idle request to all bridges */
                setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
 
-               /* Release bridges from reset state per handoff value */
-               clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+               /* Release all bridges from reset state */
+               clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
+                            ~0);
 
                /* Poll until all idleack to 0 */
                while (readl(&system_manager_base->noc_idleack))
@@ -84,31 +85,21 @@ void socfpga_bridges_reset(int enable)
                        (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
                        ;
 
-               /* Put all bridges (except NOR DDR scheduler) into reset */
-               setbits_le32(&reset_manager_base->brgmodrst,
-                            ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+               /* Reset all bridges (except NOR DDR scheduler & F2S) */
+               setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
+                            ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
+                              RSTMGR_BRGMODRST_FPGA2SOC_MASK));
 
                /* Disable NOC timeout */
                writel(0, &system_manager_base->noc_timeout);
        }
 }
 
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-       writel(0, &reset_manager_base->per1modrst);
-       /* Enable OCP first */
-       writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
-       writel(0, &reset_manager_base->per0modrst);
-}
-
 /*
  * Return non-zero if the CPU has been warm reset
  */
 int cpu_has_been_warmreset(void)
 {
-       return readl(&reset_manager_base->status) &
-               RSTMGR_L4WD_MPU_WARMRESET_MASK;
+       return readl(socfpga_get_rstmgr_addr() + RSTMGR_S10_STATUS) &
+                       RSTMGR_L4WD_MPU_WARMRESET_MASK;
 }