DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
- const void *reg;
+ unsigned long reg;
if (RSTMGR_BANK(reset) == 0)
- reg = &reset_manager_base->mpumodrst;
+ reg = RSTMGR_S10_MPUMODRST;
else if (RSTMGR_BANK(reset) == 1)
- reg = &reset_manager_base->per0modrst;
+ reg = RSTMGR_S10_PER0MODRST;
else if (RSTMGR_BANK(reset) == 2)
- reg = &reset_manager_base->per1modrst;
+ reg = RSTMGR_S10_PER1MODRST;
else if (RSTMGR_BANK(reset) == 3)
- reg = &reset_manager_base->brgmodrst;
+ reg = RSTMGR_S10_BRGMODRST;
else /* Invalid reset register, do nothing */
return;
if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ setbits_le32(socfpga_get_rstmgr_addr() + reg,
+ 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+ 1 << RSTMGR_RESET(reset));
}
/*
/* disable all except OCP and l4wd0. OCP disable later */
writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
- &reset_manager_base->per0modrst);
- writel(~l4wd0, &reset_manager_base->per0modrst);
- writel(0xffffffff, &reset_manager_base->per1modrst);
+ socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
+ writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
+ writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER1MODRST);
}
void socfpga_bridges_reset(int enable)
/* clear idle request to all bridges */
setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
- /* Release bridges from reset state per handoff value */
- clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+ /* Release all bridges from reset state */
+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
+ ~0);
/* Poll until all idleack to 0 */
while (readl(&system_manager_base->noc_idleack))
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
;
- /* Put all bridges (except NOR DDR scheduler) into reset */
- setbits_le32(&reset_manager_base->brgmodrst,
- ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+ /* Reset all bridges (except NOR DDR scheduler & F2S) */
+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
+ ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
+ RSTMGR_BRGMODRST_FPGA2SOC_MASK));
/* Disable NOC timeout */
writel(0, &system_manager_base->noc_timeout);
}
}
-/* of_reset_id: emac reset id
- * state: 0 - disable reset, !0 - enable reset
- */
-void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
-{
- u32 reset_emac;
- u32 reset_emacocp;
-
- /* hardcode this now */
- switch (of_reset_id) {
- case EMAC0_RESET:
- reset_emac = SOCFPGA_RESET(EMAC0);
- reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
- break;
- case EMAC1_RESET:
- reset_emac = SOCFPGA_RESET(EMAC1);
- reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
- break;
- case EMAC2_RESET:
- reset_emac = SOCFPGA_RESET(EMAC2);
- reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
- break;
- default:
- printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
- hang();
- break;
- }
-
- /* Reset ECC OCP first */
- socfpga_per_reset(reset_emacocp, state);
-
- /* Release the EMAC controller from reset */
- socfpga_per_reset(reset_emac, state);
-}
-
/*
- * Release peripherals from reset based on handoff
+ * Return non-zero if the CPU has been warm reset
*/
-void reset_deassert_peripherals_handoff(void)
+int cpu_has_been_warmreset(void)
{
- writel(0, &reset_manager_base->per1modrst);
- /* Enable OCP first */
- writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
- writel(0, &reset_manager_base->per0modrst);
+ return readl(socfpga_get_rstmgr_addr() + RSTMGR_S10_STATUS) &
+ RSTMGR_L4WD_MPU_WARMRESET_MASK;
}