rockchip: rk3288: Move clock CMD to SoC file

[oweals/u-boot.git] / arch / arm / mach-socfpga / reset_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index c59127456ce0cde3e0afe9f86934853d8e714f86..9a32f5abfee8bed145868bf14a6c49e35b47e607 100644 (file)
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 
@@ -62,26 +61,32 @@ void socfpga_per_reset_all(void)
        writel(0xffffffff, &reset_manager_base->per2_mod_reset);
 }
 
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-       writel(0, &reset_manager_base->per_mod_reset);
-}
-
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-void socfpga_bridges_reset(int enable)
-{
-       /* For SoCFPGA-VT, this is NOP. */
-       return;
-}
-#else
-
 #define L3REGS_REMAP_LWHPS2FPGA_MASK   0x10
 #define L3REGS_REMAP_HPS2FPGA_MASK     0x08
 #define L3REGS_REMAP_OCRAM_MASK                0x01
 
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
+{
+       u32 brgmask = 0x0;
+       u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
+
+       if (h2f)
+               brgmask |= BIT(0);
+       else
+               l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
+
+       if (lwh2f)
+               brgmask |= BIT(1);
+       else
+               l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
+
+       if (f2h)
+               brgmask |= BIT(2);
+
+       writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
+       writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
+}
+
 void socfpga_bridges_reset(int enable)
 {
        const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
@@ -90,10 +95,10 @@ void socfpga_bridges_reset(int enable)
 
        if (enable) {
                /* brdmodrst */
-               writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+               writel(0x7, &reset_manager_base->brg_mod_reset);
+               writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
        } else {
-               writel(0, &sysmgr_regs->iswgrp_handoff[0]);
-               writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+               socfpga_bridges_set_handoff_regs(false, false, false);
 
                /* Check signal from FPGA. */
                if (!fpgamgr_test_fpga_ready()) {
@@ -111,4 +116,3 @@ void socfpga_bridges_reset(int enable)
        }
        return;
 }
-#endif