Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / arch / arm / mach-socfpga / reset_manager.c

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 45b352bdfc0a5170103c33472d5fcf42e98ecb02..e0a01ed07a5aeb2cf29950a4dc37371b81ce43e5 100644 (file)
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -1,31 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
-#include <asm/arch/fpga_manager.h>
+
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/mailbox_s10.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_reset_manager *reset_manager_base =
                (void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
-void socfpga_watchdog_reset(void)
-{
-       /* assert reset for watchdog */
-       setbits_le32(&reset_manager_base->per_mod_reset,
-                    1 << RSTMGR_PERMODRST_L4WD0_LSB);
-
-       /* deassert watchdog from reset (watchdog in not running state) */
-       clrbits_le32(&reset_manager_base->per_mod_reset,
-                    1 << RSTMGR_PERMODRST_L4WD0_LSB);
-}
+#endif
 
 /*
  * Write the reset manager register to cause reset
@@ -33,8 +25,13 @@ void socfpga_watchdog_reset(void)
 void reset_cpu(ulong addr)
 {
        /* request a warm reset */
-       writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
-               &reset_manager_base->ctrl);
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+       puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+       mbox_reset_cold();
+#else
+       writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
+              &reset_manager_base->ctrl);
+#endif
        /*
         * infinite loop here as watchdog will trigger and reset
         * the processor
@@ -42,98 +39,3 @@ void reset_cpu(ulong addr)
        while (1)
                ;
 }
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-       writel(0, &reset_manager_base->per_mod_reset);
-}
-
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-void socfpga_bridges_reset(int enable)
-{
-       /* For SoCFPGA-VT, this is NOP. */
-}
-#else
-
-#define L3REGS_REMAP_LWHPS2FPGA_MASK   0x10
-#define L3REGS_REMAP_HPS2FPGA_MASK     0x08
-#define L3REGS_REMAP_OCRAM_MASK                0x01
-
-void socfpga_bridges_reset(int enable)
-{
-       const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
-                               L3REGS_REMAP_HPS2FPGA_MASK |
-                               L3REGS_REMAP_OCRAM_MASK;
-
-       if (enable) {
-               /* brdmodrst */
-               writel(0xffffffff, &reset_manager_base->brg_mod_reset);
-       } else {
-               /* Check signal from FPGA. */
-               if (fpgamgr_poll_fpga_ready()) {
-                       /* FPGA not ready. Wait for watchdog timeout. */
-                       printf("%s: fpga not ready, hanging.\n", __func__);
-                       hang();
-               }
-
-               /* brdmodrst */
-               writel(0, &reset_manager_base->brg_mod_reset);
-
-               /* Remap the bridges into memory map */
-               writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
-       }
-}
-#endif
-
-/* Change the reset state for EMAC 0 and EMAC 1 */
-void socfpga_emac_reset(int enable)
-{
-       const void *reset = &reset_manager_base->per_mod_reset;
-
-       if (enable) {
-               setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
-               setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
-       } else {
-#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
-               clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
-#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
-               clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
-#endif
-       }
-}
-
-/* SPI Master enable (its held in reset by the preloader) */
-void socfpga_spim_enable(void)
-{
-       const void *reset = &reset_manager_base->per_mod_reset;
-
-       clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
-                    (1 << RSTMGR_PERMODRST_SPIM1_LSB));
-}
-
-/* Bring UART0 out of reset. */
-void socfpga_uart0_enable(void)
-{
-       const void *reset = &reset_manager_base->per_mod_reset;
-
-       clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB);
-}
-
-/* Bring SDRAM controller out of reset. */
-void socfpga_sdram_enable(void)
-{
-       const void *reset = &reset_manager_base->per_mod_reset;
-
-       clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB);
-}
-
-/* Bring OSC1 timer out of reset. */
-void socfpga_osc1timer_enable(void)
-{
-       const void *reset = &reset_manager_base->per_mod_reset;
-
-       clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
-}