ddr: altera: Compile ALTERA SDRAM in SPL only

[oweals/u-boot.git] / arch / arm / mach-socfpga / reset_manager.c

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 29438ed533d8a7bf7178c2087557307d4673d927..e0a01ed07a5aeb2cf29950a4dc37371b81ce43e5 100644 (file)
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 
@@ -9,10 +8,16 @@
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/mailbox_s10.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_reset_manager *reset_manager_base =
                (void *)SOCFPGA_RSTMGR_ADDRESS;
+#endif
 
 /*
  * Write the reset manager register to cause reset
@@ -20,8 +25,13 @@ static const struct socfpga_reset_manager *reset_manager_base =
 void reset_cpu(ulong addr)
 {
        /* request a warm reset */
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+       puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+       mbox_reset_cold();
+#else
        writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
               &reset_manager_base->ctrl);
+#endif
        /*
         * infinite loop here as watchdog will trigger and reset
         * the processor