arm: socfpga: spl: Toggle warm reset config I/O bit

[oweals/u-boot.git] / arch / arm / mach-socfpga / reset_manager.c

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 452377c44afd94d50b0ece40aa2f4426954bc75a..1186358a71a3259715173ad95ac4fb74a656db70 100644 (file)
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -39,14 +39,17 @@ void socfpga_per_reset(u32 reset, int set)
                clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 }
 
-/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
-void socfpga_watchdog_reset(void)
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
 {
-       /* assert reset for watchdog */
-       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+       const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
 
-       /* deassert watchdog from reset (watchdog in not running state) */
-       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+       writel(~l4wd0, &reset_manager_base->per_mod_reset);
+       writel(0xffffffff, &reset_manager_base->per2_mod_reset);
 }
 
 /*
@@ -95,10 +98,10 @@ void socfpga_bridges_reset(int enable)
                writel(0xffffffff, &reset_manager_base->brg_mod_reset);
        } else {
                /* Check signal from FPGA. */
-               if (fpgamgr_poll_fpga_ready()) {
-                       /* FPGA not ready. Wait for watchdog timeout. */
-                       printf("%s: fpga not ready, hanging.\n", __func__);
-                       hang();
+               if (!fpgamgr_test_fpga_ready()) {
+                       /* FPGA not ready, do nothing. */
+                       printf("%s: FPGA not ready, aborting.\n", __func__);
+                       return;
                }
 
                /* brdmodrst */
@@ -109,43 +112,3 @@ void socfpga_bridges_reset(int enable)
        }
 }
 #endif
-
-/* Change the reset state for EMAC 0 and EMAC 1 */
-void socfpga_emac_reset(int enable)
-{
-       if (enable) {
-               socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-               socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-       } else {
-#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
-               socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
-#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
-               socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
-#endif
-       }
-}
-
-/* SPI Master enable (its held in reset by the preloader) */
-void socfpga_spim_enable(void)
-{
-       socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
-       socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-}
-
-/* Bring UART0 out of reset. */
-void socfpga_uart0_enable(void)
-{
-       socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
-}
-
-/* Bring SDRAM controller out of reset. */
-void socfpga_sdram_enable(void)
-{
-       socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-}
-
-/* Bring OSC1 timer out of reset. */
-void socfpga_osc1timer_enable(void)
-{
-       socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-}