arm: socfpga: Convert system manager from struct to defines

[oweals/u-boot.git] / arch / arm / mach-socfpga / misc_s10.c

diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 60c96090ce1c47ad2151e23d1986811f3006f38b..1849e539319d6d87ac27ed6e5039d99e354f807b 100644 (file)
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -6,6 +6,7 @@
 
 #include <altera.h>
 #include <common.h>
+#include <env.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <miiphy.h>
@@ -16,14 +17,12 @@
 #include <asm/arch/misc.h>
 #include <asm/pl310.h>
 #include <linux/libfdt.h>
+#include <asm/arch/mailbox_s10.h>
 
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct socfpga_system_manager *sysmgr_regs =
-       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /*
  * FPGA programming support for SoC FPGA Stratix 10
  */
@@ -66,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
        else
                return -EINVAL;
 
-       clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
-                       SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
-                       modereg);
+       clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC0 +
+                       gmac_index,
+                       SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
 
        return 0;
 }
@@ -152,5 +151,16 @@ int arch_early_init_r(void)
 
 void do_bridge_reset(int enable, unsigned int mask)
 {
+       /* Check FPGA status before bridge enable */
+       if (enable) {
+               int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
+
+               if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+                       ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
+
+               if (ret)
+                       return;
+       }
+
        socfpga_bridges_reset(enable);
 }