(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
/*
- * DesignWare Ethernet initialization
+ * FPGA programming support for SoC FPGA Cyclone V
*/
-#ifdef CONFIG_ETH_DESIGNWARE
-void dwmac_deassert_reset(const unsigned int of_reset_id,
- const u32 phymode)
-{
- u32 physhift, reset;
-
- if (of_reset_id == EMAC0_RESET) {
- physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
- reset = SOCFPGA_RESET(EMAC0);
- } else if (of_reset_id == EMAC1_RESET) {
- physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
- reset = SOCFPGA_RESET(EMAC1);
- } else {
- printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
- return;
- }
-
- /* configure to PHY interface select choosed */
- clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
- phymode << physhift);
-
- /* Release the EMAC controller from reset */
- socfpga_per_reset(reset, 0);
-}
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- return 0;
- }
-
- if (!strcmp(phymode, "rgmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- return 0;
- }
-
- if (!strcmp(phymode, "rmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static int socfpga_eth_reset(void)
-{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 phy_modereg;
- int nodes[2]; /* Max. two GMACs */
- int ret, count;
- int i, node;
-
- /* Put both GMACs into RESET state. */
- socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
- socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
- "#reset-cells", 1, 0,
- &args);
- if (ret || (args.args_count != 1)) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
-
- dwmac_deassert_reset(args.args[0], phy_modereg);
- }
-
- return 0;
-}
-#else
-static int socfpga_eth_reset(void)
-{
- return 0;
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
};
-#endif
static const struct {
const u16 pn;
env_set("bootmode", bsel_str[bsel].mode);
if (fpga_id >= 0)
env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
- return socfpga_eth_reset();
+ return 0;
}
#endif
writel(0x1, &nic301_regs->sdrdata);
}
+void socfpga_sdram_remap_zero(void)
+{
+ u32 remap;
+
+ socfpga_nic301_slave_ns();
+
+ /*
+ * Private components security:
+ * U-Boot : configure private timer, global timer and cpu component
+ * access as non secure for kernel stage (as required by Linux)
+ */
+ setbits_le32(&scu_regs->sacr, 0xfff);
+
+ /* Configure the L2 controller to make SDRAM start at 0 */
+ remap = 0x1; /* remap.mpuzero */
+ /* Keep fpga bridge enabled when running from FPGA onchip RAM */
+ if (socfpga_is_booting_from_fpga())
+ remap |= 0x8; /* remap.hps2fpga */
+ writel(remap, &nic301_regs->remap);
+
+ writel(0x1, &pl310->pl310_addr_filter_start);
+}
+
static u32 iswgrp_handoff[8];
int arch_early_init_r(void)
socfpga_bridges_reset(1);
- socfpga_nic301_slave_ns();
-
- /*
- * Private components security:
- * U-Boot : configure private timer, global timer and cpu component
- * access as non secure for kernel stage (as required by Linux)
- */
- setbits_le32(&scu_regs->sacr, 0xfff);
-
- /* Configure the L2 controller to make SDRAM start at 0 */
- writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
- writel(0x1, &pl310->pl310_addr_filter_start);
+ socfpga_sdram_remap_zero();
/* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
+ socfpga_fpga_add(&altera_fpga[0]);
#ifdef CONFIG_DESIGNWARE_SPI
/* Get Designware SPI controller out of reset */
: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
}
-static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+void do_bridge_reset(int enable)
{
- if (argc != 2)
- return CMD_RET_USAGE;
-
- argv++;
-
- switch (*argv[0]) {
- case 'e': /* Enable */
+ if (enable) {
writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
socfpga_sdram_apply_static_cfg();
writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
writel(iswgrp_handoff[1], &nic301_regs->remap);
- break;
- case 'd': /* Disable */
+ } else {
writel(0, &sysmgr_regs->fpgaintfgrp_module);
writel(0, &sdr_ctrl->fpgaport_rst);
socfpga_sdram_apply_static_cfg();
writel(0, &reset_manager_base->brg_mod_reset);
writel(1, &nic301_regs->remap);
- break;
- default:
- return CMD_RET_USAGE;
}
-
- return 0;
}
-
-U_BOOT_CMD(
- bridge, 2, 1, do_bridge,
- "SoCFPGA HPS FPGA bridge control",
- "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
- "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
- ""
-);
#endif
projects / oweals / u-boot.git / blobdiff