arm: am57xx: cl-som-am57x: remove board support

[oweals/u-boot.git] / arch / arm / mach-socfpga / misc_gen5.c

diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 5fa40937c405da8c0e07ff1b5a9739347a9d84af..6e11ba6cb24e00c4a93e0e5d672be6c82c23e98c 100644 (file)
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -35,46 +35,24 @@ static struct scu_registers *scu_regs =
        (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
 /*
- * DesignWare Ethernet initialization
+ * FPGA programming support for SoC FPGA Cyclone V
  */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
-{
-       u32 physhift, reset;
-
-       if (of_reset_id == EMAC0_RESET) {
-               physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
-               reset = SOCFPGA_RESET(EMAC0);
-       } else if (of_reset_id == EMAC1_RESET) {
-               physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
-               reset = SOCFPGA_RESET(EMAC1);
-       } else {
-               printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
-               return;
-       }
-
-       /* configure to PHY interface select choosed */
-       clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
-                       SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
-                       phymode << physhift);
-
-       /* Release the EMAC controller from reset */
-       socfpga_per_reset(reset, 0);
-}
-
-static int socfpga_eth_reset(void)
-{
-       /* Put all GMACs into RESET state. */
-       socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-       socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-       return socfpga_eth_reset_common(gen5_dwmac_reset);
-};
-#else
-static int socfpga_eth_reset(void)
-{
-       return 0;
+static Altera_desc altera_fpga[] = {
+       {
+               /* Family */
+               Altera_SoCFPGA,
+               /* Interface type */
+               fast_passive_parallel,
+               /* No limitation as additional data will be ignored */
+               -1,
+               /* No device function table */
+               NULL,
+               /* Base interface address specified in driver */
+               NULL,
+               /* No cookie implementation */
+               0
+       },
 };
-#endif
 
 static const struct {
        const u16       pn;
@@ -158,7 +136,7 @@ int arch_misc_init(void)
        env_set("bootmode", bsel_str[bsel].mode);
        if (fpga_id >= 0)
                env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
-       return socfpga_eth_reset();
+       return 0;
 }
 #endif
 
@@ -221,7 +199,7 @@ int arch_early_init_r(void)
        socfpga_sdram_remap_zero();
 
        /* Add device descriptor to FPGA device table */
-       socfpga_fpga_add();
+       socfpga_fpga_add(&altera_fpga[0]);
 
 #ifdef CONFIG_DESIGNWARE_SPI
        /* Get Designware SPI controller out of reset */