ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable

[oweals/u-boot.git] / arch / arm / mach-socfpga / misc_gen5.c

diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 6e11ba6cb24e00c4a93e0e5d672be6c82c23e98c..36f00aee31a970430f967eae49f7f6ca15be767f 100644 (file)
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <env.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <linux/libfdt.h>
@@ -201,16 +202,6 @@ int arch_early_init_r(void)
        /* Add device descriptor to FPGA device table */
        socfpga_fpga_add(&altera_fpga[0]);
 
-#ifdef CONFIG_DESIGNWARE_SPI
-       /* Get Designware SPI controller out of reset */
-       socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
-       socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-#endif
-
-#ifdef CONFIG_NAND_DENALI
-       socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
-#endif
-
        return 0;
 }
 
@@ -220,48 +211,27 @@ static struct socfpga_reset_manager *reset_manager_base =
 static struct socfpga_sdr_ctrl *sdr_ctrl =
        (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
-static void socfpga_sdram_apply_static_cfg(void)
+void do_bridge_reset(int enable, unsigned int mask)
 {
-       const u32 applymask = 0x8;
-       u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
-
-       /*
-        * SDRAM staticcfg register specific:
-        * When applying the register setting, the CPU must not access
-        * SDRAM. Luckily for us, we can abuse i-cache here to help us
-        * circumvent the SDRAM access issue. The idea is to make sure
-        * that the code is in one full i-cache line by branching past
-        * it and back. Once it is in the i-cache, we execute the core
-        * of the code and apply the register settings.
-        *
-        * The code below uses 7 instructions, while the Cortex-A9 has
-        * 32-byte cachelines, thus the limit is 8 instructions total.
-        */
-       asm volatile(
-               ".align 5                       \n"
-               "       b       2f              \n"
-               "1:     str     %0,     [%1]    \n"
-               "       dsb                     \n"
-               "       isb                     \n"
-               "       b       3f              \n"
-               "2:     b       1b              \n"
-               "3:     nop                     \n"
-       : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
-}
+       int i;
 
-void do_bridge_reset(int enable)
-{
        if (enable) {
+               socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
+                                                !(mask & BIT(1)),
+                                                !(mask & BIT(2)));
+               for (i = 0; i < 2; i++) {       /* Reload SW setting cache */
+                       iswgrp_handoff[i] =
+                               readl(&sysmgr_regs->iswgrp_handoff[i]);
+               }
+
                writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
-               socfpga_sdram_apply_static_cfg();
                writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
                writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
                writel(iswgrp_handoff[1], &nic301_regs->remap);
        } else {
                writel(0, &sysmgr_regs->fpgaintfgrp_module);
                writel(0, &sdr_ctrl->fpgaport_rst);
-               socfpga_sdram_apply_static_cfg();
-               writel(0, &reset_manager_base->brg_mod_reset);
+               writel(0x7, &reset_manager_base->brg_mod_reset);
                writel(1, &nic301_regs->remap);
        }
 }