Merge git://git.denx.de/u-boot-marvell

[oweals/u-boot.git] / arch / arm / mach-socfpga / misc_arria10.c

diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 284e076ad661c7dc1019b1df517e453799376145..63b8c75d31d134053ac521c62bded724315d8485 100644 (file)
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -28,17 +28,35 @@
 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7  0x78
 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3  0x98
 
+static struct socfpga_system_manager *sysmgr_regs =
+       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+       {
+               /* Family */
+               Altera_SoCFPGA,
+               /* Interface type */
+               fast_passive_parallel,
+               /* No limitation as additional data will be ignored */
+               -1,
+               /* No device function table */
+               NULL,
+               /* Base interface address specified in driver */
+               NULL,
+               /* No cookie implementation */
+               0
+       },
+};
+
 #if defined(CONFIG_SPL_BUILD)
 static struct pl310_regs *const pl310 =
        (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
        (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-#endif
-
-static struct socfpga_system_manager *sysmgr_regs =
-       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-#if defined(CONFIG_SPL_BUILD)
 /*
 + * This function initializes security policies to be consistent across
 + * all logic units in the Arria 10.
@@ -46,7 +64,7 @@ static struct socfpga_system_manager *sysmgr_regs =
 + * The idea is to set all security policies to be normal, nonsecure
 + * for all units.
 + */
-static void initialize_security_policies(void)
+void socfpga_init_security_policies(void)
 {
        /* Put OCRAM in non-secure */
        writel(0x003f0000, &noc_fw_ocram_base->region0);
@@ -66,24 +84,20 @@ static void initialize_security_policies(void)
        writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
 }
 
-int arch_early_init_r(void)
+void socfpga_sdram_remap_zero(void)
 {
-       initialize_security_policies();
-
        /* Configure the L2 controller to make SDRAM start at 0 */
        writel(0x1, &pl310->pl310_addr_filter_start);
-
-       /* assert reset to all except L4WD0 and L4TIMER0 */
-       socfpga_per_reset_all();
-
-       return 0;
 }
-#else
+#endif
+
 int arch_early_init_r(void)
 {
+       /* Add device descriptor to FPGA device table */
+       socfpga_fpga_add(&altera_fpga[0]);
+
        return 0;
 }
-#endif
 
 /*
  * Print CPU information