Merge branch 'master' of git://git.denx.de/u-boot-usb

[oweals/u-boot.git] / arch / arm / mach-socfpga / misc.c

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index e1ea8eb73e33ecd004f8a99adfa68b7f27cff8c8..49dadd4c3d8f6321777e3466c40c1fde382f7673 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -48,19 +48,37 @@ int dram_init(void)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        dcache_enable();
 #endif
 }
 
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
+{
+       struct udevice *dev;
+
+       if (uclass_get_device(UCLASS_CACHE, 0, &dev))
+               pr_err("cache controller driver NOT found!\n");
+}
+
+void v7_outer_cache_disable(void)
 {
        /* Disable the L2 cache */
        clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void socfpga_pl310_clear(void)
+{
+       u32 mask = 0xff, ena = 0;
+
+       icache_enable();
+
+       /* Disable the L2 cache */
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
        writel(0x0, &pl310->pl310_tag_latency_ctrl);
        writel(0x10, &pl310->pl310_data_latency_ctrl);
@@ -72,11 +90,37 @@ void v7_outer_cache_enable(void)
                     L310_SHARED_ATT_OVERRIDE_ENABLE);
 
        /* Enable the L2 cache */
-       setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
+       ena = readl(&pl310->pl310_ctrl);
+       ena |= L2X0_CTRL_EN;
+
+       /*
+        * Invalidate the PL310 L2 cache. Keep the invalidation code
+        * entirely in L1 I-cache to avoid any bus traffic through
+        * the L2.
+        */
+       asm volatile(
+               ".align 5                       \n"
+               "       b       3f              \n"
+               "1:     str     %1,     [%4]    \n"
+               "       dsb                     \n"
+               "       isb                     \n"
+               "       str     %0,     [%2]    \n"
+               "       dsb                     \n"
+               "       isb                     \n"
+               "2:     ldr     %0,     [%2]    \n"
+               "       cmp     %0,     #0      \n"
+               "       bne     2b              \n"
+               "       str     %0,     [%3]    \n"
+               "       dsb                     \n"
+               "       isb                     \n"
+               "       b       4f              \n"
+               "3:     b       1b              \n"
+               "4:     nop                     \n"
+       : "+r"(mask), "+r"(ena)
+       : "r"(&pl310->pl310_inv_way),
+         "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
+       : "memory", "cc");
 
-void v7_outer_cache_disable(void)
-{
        /* Disable the L2 cache */
        clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }