ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable

[oweals/u-boot.git] / arch / arm / mach-socfpga / include / mach / fpga_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696830c502e3ba06265bd6f356c4afd31fdb..62249b3695e1d6db617ca76d8984c8ea26023600 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -1,10 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  * All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
+#include <asm/cache.h>
+#include <altera.h>
+#include <image.h>
+
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
@@ -52,6 +55,10 @@
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK             BIT(24)
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB                  16
 
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED       0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED         0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH            0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE              0x8001
 #ifndef __ASSEMBLY__
 
 struct socfpga_fpga_manager {
@@ -89,12 +96,40 @@ struct socfpga_fpga_manager {
        u32  imgcfg_fifo_status;
 };
 
+enum rbf_type {
+       unknown,
+       periph_section,
+       core_section
+};
+
+enum rbf_security {
+       invalid,
+       unencrypted,
+       encrypted
+};
+
+struct rbf_info {
+       enum rbf_type section;
+       enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+       fpga_fs_info *fpga_fsinfo;
+       u32 remaining;
+       u32 offset;
+       struct rbf_info rbfinfo;
+};
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
-
+const char *get_fpga_filename(void);
+int is_fpgamgr_early_user_mode(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+                 u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
 #endif /* __ASSEMBLY__ */
 
 #endif /* _FPGA_MANAGER_ARRIA10_H_ */