ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable

[oweals/u-boot.git] / arch / arm / mach-socfpga / include / mach / base_addr_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4da71df4f88bf0a17e31ed032ca960970a..929c413e03922926a31d44d3ef307d3c1cdfdf89 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
  */
 
 #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
@@ -29,17 +28,23 @@
 #define SOCFPGA_MPUL2_ADDRESS                  0xfffff000
 #define SOCFPGA_I2C0_ADDRESS                   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS                   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS                   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS                   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS                   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS              0xff8c3000
 #define SOCFPGA_UART0_ADDRESS                  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS             0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS             0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS                 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS                 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS                    0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST           0xffd11000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS          0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS     0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS                0xffd13400
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST            0xffd13500
 
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */