arm: dts: am437x-gp-evm: Add some nodes to u-boot.dtsi

[oweals/u-boot.git] / arch / arm / mach-socfpga / clock_manager.c

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 9f3c643df88998fab2ef0871e5fa6db050666ab7..dbb10ecb681cec7795a88d15a32f9f9f35488e3c 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,18 +10,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 void cm_wait_for_lock(u32 mask)
 {
        u32 inter_val;
        u32 retry = 0;
        do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-               inter_val = readl(&clock_manager_base->inter) & mask;
+               inter_val = readl(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_INTER) & mask;
 #else
-               inter_val = readl(&clock_manager_base->stat) & mask;
+               inter_val = readl(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_STAT) & mask;
 #endif
                /* Wait for stable lock */
                if (inter_val == mask)
@@ -36,8 +35,9 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-       return wait_for_bit_le32(&clock_manager_base->stat,
-                                CLKMGR_STAT_BUSY, false, 20000, false);
+       return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
+                                CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
+                                false);
 }
 
 int set_cpu_clk_info(void)