rockchip: rk3288-veyron: Migrate "u-boot, boot0" to "u-boot, spl-boot-order"
[oweals/u-boot.git] / arch / arm / mach-socfpga / Makefile
index 69bdb84d4fc786582684404c8c799c14d7009832..e66720447f85e22d9c4c97f6ffb24e005e09dc37 100644 (file)
@@ -9,7 +9,6 @@ obj-y   += board.o
 obj-y  += clock_manager.o
 obj-y  += misc.o
 obj-y  += reset_manager.o
-obj-y  += timer.o
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += clock_manager_gen5.o
@@ -17,6 +16,7 @@ obj-y += misc_gen5.o
 obj-y  += reset_manager_gen5.o
 obj-y  += scan_manager.o
 obj-y  += system_manager_gen5.o
+obj-y  += timer.o
 obj-y  += wrap_pll_config.o
 obj-y  += fpga_manager.o
 endif
@@ -30,17 +30,30 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += mailbox_s10.o
+obj-y  += misc_s10.o
+obj-y  += mmu-arm64_s10.o
 obj-y  += reset_manager_s10.o
+obj-y  += system_manager_s10.o
+obj-y  += timer_s10.o
+obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
+
 ifdef CONFIG_SPL_BUILD
-obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += spl_gen5.o
 obj-y  += freeze_controller.o
 obj-y  += wrap_iocsr_config.o
 obj-y  += wrap_pinmux_config.o
 obj-y  += wrap_sdram_config.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y  += spl_a10.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += spl_s10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5