arm: socfpga: Add pinmux for Arria 10

[oweals/u-boot.git] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index e56b3db1158987ecacca8ab9a9d239bc621311e2..f6e5773272d64ae81f3274414f0ca136191f3cc7 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -43,6 +43,7 @@ config TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_GEN5
        bool
+       select ALTERA_SDRAM
 
 choice
        prompt "Altera SOCFPGA board select"
@@ -56,8 +57,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
        bool "Altera SOCFPGA SoCDK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_DENX_MCVEVK
-       bool "DENX MCVEVK (Cyclone V)"
+config TARGET_SOCFPGA_ARIES_MCVEVK
+       bool "Aries MCVEVK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_EBV_SOCRATES
@@ -81,6 +82,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
        bool "Terasic DE0-Nano-Atlas (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+       bool "Terasic DE10-Nano (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE1_SOC
        bool "Terasic DE1-SoC (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -96,8 +101,9 @@ config SYS_BOARD
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "is1" if TARGET_SOCFPGA_IS1
-       default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "sr1500" if TARGET_SOCFPGA_SR1500
@@ -106,11 +112,12 @@ config SYS_BOARD
 config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
-       default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
        default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
@@ -121,8 +128,9 @@ config SYS_CONFIG_NAME
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "socfpga_is1" if TARGET_SOCFPGA_IS1
-       default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500