Convert CONFIG_SPL_LIBDISK_SUPPORT to Kconfig

[oweals/u-boot.git] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index e46c3489959c57ed39f701fd4db7201fc8fdb3d3..ac5af9bc3a84895881bdfe510adf0d1672a65d91 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,28 +1,96 @@
 if ARCH_SOCFPGA
 
+config SPL_LIBCOMMON_SUPPORT
+       default y
+
+config SPL_LIBDISK_SUPPORT
+       default y
+
+config TARGET_SOCFPGA_ARRIA5
+       bool
+       select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_CYCLONE5
+       bool
+       select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+       bool
+
 choice
        prompt "Altera SOCFPGA board select"
        optional
 
-config TARGET_SOCFPGA_ARRIA5
-       bool "Altera SOCFPGA Arria V"
+config TARGET_SOCFPGA_ARRIA5_SOCDK
+       bool "Altera SOCFPGA SoCDK (Arria V)"
+       select TARGET_SOCFPGA_ARRIA5
 
-config TARGET_SOCFPGA_CYCLONE5
-       bool "Altera SOCFPGA Cyclone V"
+config TARGET_SOCFPGA_CYCLONE5_SOCDK
+       bool "Altera SOCFPGA SoCDK (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_DENX_MCVEVK
+       bool "DENX MCVEVK (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_EBV_SOCRATES
+       bool "EBV SoCrates (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_IS1
+       bool "IS1 (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       bool "samtec VIN|ING FPGA (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SR1500
+       bool "SR1500 (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE0_NANO
+       bool "Terasic DE0-Nano-Atlas (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_SOCKIT
+       bool "Terasic SoCkit (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
 
 endchoice
 
 config SYS_BOARD
-       default "socfpga"
+       default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+       default "is1" if TARGET_SOCFPGA_IS1
+       default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+       default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "sr1500" if TARGET_SOCFPGA_SR1500
+       default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
-       default "altera"
+       default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+       default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
        default "socfpga"
 
 config SYS_CONFIG_NAME
-       default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5
-       default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5
+       default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+       default "socfpga_is1" if TARGET_SOCFPGA_IS1
+       default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+       default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif