arm: socfpga: agilex: Enable Agilex SoC build

[oweals/u-boot.git] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index afc38d5da9e72a3091b40964d31d1aa4c5b4b117..969698c83fa576fa8a8034aa8d95476049bd3df4 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,37 +1,42 @@
 if ARCH_SOCFPGA
 
-config SPL_LIBCOMMON_SUPPORT
-       default y
+config ERR_PTR_OFFSET
+       default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
 
-config SPL_LIBDISK_SUPPORT
-       default y
+config NR_DRAM_BANKS
+       default 1
 
-config SPL_LIBGENERIC_SUPPORT
-       default y
+config SPL_SIZE_LIMIT
+       default 0x10000 if TARGET_SOCFPGA_GEN5
 
-config SPL_MMC_SUPPORT
-       default y if DM_MMC
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+       default 0x200 if TARGET_SOCFPGA_GEN5
 
-config SPL_NAND_SUPPORT
-       default y if SPL_NAND_DENALI
+config SPL_STACK_R_ADDR
+       default 0x00800000 if TARGET_SOCFPGA_GEN5
 
-config SPL_SERIAL_SUPPORT
-       default y
+config SPL_SYS_MALLOC_F_LEN
+       default 0x800 if TARGET_SOCFPGA_GEN5
 
-config SPL_SPI_FLASH_SUPPORT
-       default y if SPL_SPI_SUPPORT
-
-config SPL_SPI_SUPPORT
-       default y if DM_SPI
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+       default 0xa2
 
-config SPL_WATCHDOG_SUPPORT
-       default y
+config SYS_MALLOC_F_LEN
+       default 0x2000 if TARGET_SOCFPGA_ARRIA10
+       default 0x2000 if TARGET_SOCFPGA_GEN5
 
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
-       default y
+config SYS_TEXT_BASE
+       default 0x01000040 if TARGET_SOCFPGA_ARRIA10
+       default 0x01000040 if TARGET_SOCFPGA_GEN5
 
-config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
-       default 0xa2
+config TARGET_SOCFPGA_AGILEX
+       bool
+       select ARMV8_MULTIENTRY
+       select ARMV8_SET_SMPEN
+       select ARMV8_SPIN_TABLE
+       select CLK
+       select NCORE_CACHE
+       select SPL_CLK if SPL
 
 config TARGET_SOCFPGA_ARRIA5
        bool
@@ -39,7 +44,20 @@ config TARGET_SOCFPGA_ARRIA5
 
 config TARGET_SOCFPGA_ARRIA10
        bool
+       select SPL_ALTERA_SDRAM
        select SPL_BOARD_INIT if SPL
+       select CLK
+       select SPL_CLK if SPL
+       select DM_I2C
+       select DM_RESET
+       select SPL_DM_RESET if SPL
+       select REGMAP
+       select SPL_REGMAP if SPL
+       select SYSCON
+       select SPL_SYSCON if SPL
+       select ETH_DESIGNWARE_SOCFPGA
+       imply FPGA_SOCFPGA
+       imply SPL_USE_TINY_PRINTF
 
 config TARGET_SOCFPGA_CYCLONE5
        bool
@@ -47,12 +65,33 @@ config TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_GEN5
        bool
-       select ALTERA_SDRAM
+       select SPL_ALTERA_SDRAM
+       imply FPGA_SOCFPGA
+       imply SPL_SIZE_LIMIT_SUBTRACT_GD
+       imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+       imply SPL_STACK_R
+       imply SPL_SYS_MALLOC_SIMPLE
+       imply SPL_USE_TINY_PRINTF
+
+config TARGET_SOCFPGA_STRATIX10
+       bool
+       select ARMV8_MULTIENTRY
+       select ARMV8_SET_SMPEN
+       select ARMV8_SPIN_TABLE
+       select FPGA_STRATIX10
 
 choice
        prompt "Altera SOCFPGA board select"
        optional
 
+config TARGET_SOCFPGA_AGILEX_SOCDK
+       bool "Intel SOCFPGA SoCDK (Agilex)"
+       select TARGET_SOCFPGA_AGILEX
+
+config TARGET_SOCFPGA_ARIES_MCVEVK
+       bool "Aries MCVEVK (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_ARRIA10_SOCDK
        bool "Altera SOCFPGA SoCDK (Arria 10)"
        select TARGET_SOCFPGA_ARRIA10
@@ -65,10 +104,6 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
        bool "Altera SOCFPGA SoCDK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_ARIES_MCVEVK
-       bool "Aries MCVEVK (Cyclone V)"
-       select TARGET_SOCFPGA_CYCLONE5
-
 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        bool "Devboards DBM-SoC1 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -81,8 +116,8 @@ config TARGET_SOCFPGA_IS1
        bool "IS1 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
-       bool "samtec VIN|ING FPGA (Cyclone V)"
+config TARGET_SOCFPGA_SOFTING_VINING_FPGA
+       bool "Softing VIN|ING FPGA (Cyclone V)"
        select BOARD_LATE_INIT
        select TARGET_SOCFPGA_CYCLONE5
 
@@ -90,6 +125,10 @@ config TARGET_SOCFPGA_SR1500
        bool "SR1500 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+       bool "Intel SOCFPGA SoCDK (Stratix 10)"
+       select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
        bool "Terasic DE0-Nano-Atlas (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -109,6 +148,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 endchoice
 
 config SYS_BOARD
+       default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -121,16 +161,19 @@ config SYS_BOARD
        default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "sr1500" if TARGET_SOCFPGA_SR1500
-       default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
+       default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
+       default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
        default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
-       default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
@@ -140,6 +183,7 @@ config SYS_SOC
        default "socfpga"
 
 config SYS_CONFIG_NAME
+       default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -152,6 +196,7 @@ config SYS_CONFIG_NAME
        default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
-       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
+       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 endif