if ARCH_SOCFPGA
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y if DM_MMC
+
+config SPL_NAND_SUPPORT
+ default y if SPL_NAND_DENALI
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config SPL_SPI_FLASH_SUPPORT
+ default y if SPL_SPI_SUPPORT
+
+config SPL_SPI_SUPPORT
+ default y if DM_SPI
+
+config SPL_WATCHDOG_SUPPORT
+ default y
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ default y
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+ default 0xa2
+
config TARGET_SOCFPGA_ARRIA5
bool
+ select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_ARRIA10
+ bool
+ select SPL_BOARD_INIT if SPL
config TARGET_SOCFPGA_CYCLONE5
bool
+ select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+ bool
+ select ALTERA_SDRAM
choice
prompt "Altera SOCFPGA board select"
optional
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+ bool "Altera SOCFPGA SoCDK (Arria 10)"
+ select TARGET_SOCFPGA_ARRIA10
+
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_ARIES_MCVEVK
+ bool "Aries MCVEVK (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_EBV_SOCRATES
+ bool "EBV SoCrates (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_IS1
+ bool "IS1 (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+ bool "samtec VIN|ING FPGA (Cyclone V)"
+ select BOARD_LATE_INIT
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SR1500
+ bool "SR1500 (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE0_NANO
+ bool "Terasic DE0-Nano-Atlas (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+ bool "Terasic DE10-Nano (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE1_SOC
+ bool "Terasic DE1-SoC (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_SOCKIT
+ bool "Terasic SoCkit (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
endchoice
config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+ default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+ default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+ default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "is1" if TARGET_SOCFPGA_IS1
+ default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "sr1500" if TARGET_SOCFPGA_SR1500
+ default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+ default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+ default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+ default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+ default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
- default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
- default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+ default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+ default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+ default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+ default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "socfpga_is1" if TARGET_SOCFPGA_IS1
+ default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+ default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif