rockchip: rk3399: move SoC setting into arch_cpu_init()
[oweals/u-boot.git] / arch / arm / mach-rockchip / rk3399 / rk3399.c
index a7ccd4f3ed2c6177045883ba9a69bc638f0209a4..ead878b3fdcbf960812f8dde9cac4f16f50e3011 100644 (file)
@@ -38,6 +38,35 @@ static struct mm_region rk3399_mem_map[] = {
 
 struct mm_region *mem_map = rk3399_mem_map;
 
+#ifdef CONFIG_SPL_BUILD
+
+#define TIMER_END_COUNT_L      0x00
+#define TIMER_END_COUNT_H      0x04
+#define TIMER_INIT_COUNT_L     0x10
+#define TIMER_INIT_COUNT_H     0x14
+#define TIMER_CONTROL_REG      0x1c
+
+#define TIMER_EN       0x1
+#define TIMER_FMODE    BIT(0)
+#define TIMER_RMODE    BIT(1)
+
+void rockchip_stimer_init(void)
+{
+       /* If Timer already enabled, don't re-init it */
+       u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+
+       if (reg & TIMER_EN)
+               return;
+
+       writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
+       writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
+       writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
+       writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
+       writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
+              TIMER_CONTROL_REG);
+}
+#endif
+
 int dram_init_banksize(void)
 {
        size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
@@ -51,11 +80,28 @@ int dram_init_banksize(void)
 
 int arch_cpu_init(void)
 {
-       /* We do some SoC one time setting here. */
-       struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 
-       /* Emmc clock generator: disable the clock multipilier */
+#ifdef CONFIG_SPL_BUILD
+       struct rk3399_pmusgrf_regs *sgrf;
+       struct rk3399_grf_regs *grf;
+
+       /*
+        * Disable DDR and SRAM security regions.
+        *
+        * As we are entered from the BootROM, the region from
+        * 0x0 through 0xfffff (i.e. the first MB of memory) will
+        * be protected. This will cause issues with the DW_MMC
+        * driver, which tries to DMA from/to the stack (likely)
+        * located in this range.
+        */
+       sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
+       rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
+       rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
+
+       /*  eMMC clock generator: disable the clock multipilier */
+       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
        rk_clrreg(&grf->emmccore_con[11], 0x0ff);
+#endif
 
        return 0;
 }
@@ -80,6 +126,14 @@ void board_debug_uart_init(void)
        rk_clrsetreg(&grf->gpio2c_iomux,
                     GRF_GPIO2C1_SEL_MASK,
                     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
+       /* Enable early UART3 on the RK3399 */
+       rk_clrsetreg(&grf->gpio3b_iomux,
+                    GRF_GPIO3B6_SEL_MASK,
+                    GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
+       rk_clrsetreg(&grf->gpio3b_iomux,
+                    GRF_GPIO3B7_SEL_MASK,
+                    GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
 #else
 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
        rk_setreg(&grf->io_vsel, 1 << 0);
@@ -109,3 +163,53 @@ void board_debug_uart_init(void)
 #endif
 }
 #endif
+
+#ifdef CONFIG_SPL_BUILD
+const char *spl_decode_boot_device(u32 boot_device)
+{
+       int i;
+       static const struct {
+               u32 boot_device;
+               const char *ofpath;
+       } spl_boot_devices_tbl[] = {
+               { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
+               { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
+               { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
+       };
+
+       for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
+               if (spl_boot_devices_tbl[i].boot_device == boot_device)
+                       return spl_boot_devices_tbl[i].ofpath;
+
+       return NULL;
+}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+       void *blob = spl_image->fdt_addr;
+       const char *boot_ofpath;
+       int chosen;
+
+       /*
+        * Inject the ofpath of the device the full U-Boot (or Linux in
+        * Falcon-mode) was booted from into the FDT, if a FDT has been
+        * loaded at the same time.
+        */
+       if (!blob)
+               return;
+
+       boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
+       if (!boot_ofpath) {
+               pr_err("%s: could not map boot_device to ofpath\n", __func__);
+               return;
+       }
+
+       chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
+       if (chosen < 0) {
+               pr_err("%s: could not find/create '/chosen'\n", __func__);
+               return;
+       }
+       fdt_setprop_string(blob, chosen,
+                          "u-boot,spl-boot-device", boot_ofpath);
+}
+#endif