+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <ram.h>
+#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
DECLARE_GLOBAL_DATA_PTR;
-#define GRF_BASE 0x11000000
-
-static void setup_boot_mode(void)
-{
- struct rk322x_grf *const grf = (void *)GRF_BASE;
- int boot_mode = readl(&grf->os_reg[4]);
-
- debug("boot mode %x.\n", boot_mode);
-
- /* Clear boot mode */
- writel(BOOT_NORMAL, &grf->os_reg[4]);
-
- switch (boot_mode) {
- case BOOT_FASTBOOT:
- printf("enter fastboot!\n");
- setenv("preboot", "setenv preboot; fastboot usb0");
- break;
- case BOOT_UMS:
- printf("enter UMS!\n");
- setenv("preboot", "setenv preboot; ums mmc 0");
- break;
- }
-}
-
__weak int rk_board_late_init(void)
{
return 0;
/* Enable early UART2 channel 1 on the RK322x */
#define GRF_BASE 0x11000000
struct rk322x_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+ };
+ enum {
+ CON_IOMUX_UART2SEL_SHIFT= 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ };
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B2_MASK,
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+ /*
+ * The integrated macphy is enabled by default, disable it
+ * for saving power consuming.
+ */
+ rk_clrsetreg(&grf->macphy_con[0],
+ MACPHY_CFG_ENABLE_MASK,
+ 0 << MACPHY_CFG_ENABLE_SHIFT);
+
return 0;
}
int dram_init_banksize(void)
{
- /* Reserve 0x200000 for OPTEE */
- gd->bd->bi_dram[0].start = 0x60000000;
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
- gd->bd->bi_dram[1].start = 0x6a400000;
- gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].start;
+ /* Reserve 0x200000 for OPTEE */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ + gd->bd->bi_dram[0].size + 0x200000;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ + gd->ram_size - gd->bd->bi_dram[1].start;
return 0;
}
return 0;
}
#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT)
+int fastboot_set_reboot_flag(void)
+{
+ struct rk322x_grf *grf;
+
+ printf("Setting reboot to fastboot flag ...\n");
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ /* Set boot mode to fastboot */
+ writel(BOOT_FASTBOOT, &grf->os_reg[0]);
+
+ return 0;
+}
+#endif