+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
*/
-
#include <common.h>
#include <clk.h>
+#include <cpu_func.h>
#include <dm.h>
+#include <init.h>
#include <ram.h>
+#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/boot_mode.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
+#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+__weak int rk_board_late_init(void)
{
return 0;
}
-int dram_init(void)
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+int board_init(void)
{
- struct ram_info ram;
- struct udevice *dev;
int ret;
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
- ret = ram_get_info(dev, &ram);
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
- debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
- gd->ram_size = ram.size;
+#ifdef CONFIG_DM_REGULATOR
+ ret = regulators_enable_boot_on(false);
+ if (ret)
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
}
#endif
-void lowlevel_init(void)
-{
-}
+#if defined(CONFIG_USB_GADGET)
+#include <usb.h>
+
+#if defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb/dwc2_udc.h>
-static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+static struct dwc2_plat_otg_data otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
{
- static const struct {
- char *name;
- int id;
- } clks[] = {
- { "osc", CLK_OSC },
- { "apll", CLK_ARM },
- { "dpll", CLK_DDR },
- { "cpll", CLK_CODEC },
- { "gpll", CLK_GENERAL },
-#ifdef CONFIG_ROCKCHIP_RK3036
- { "mpll", CLK_NEW },
-#else
- { "npll", CLK_NEW },
-#endif
- };
- int ret, i;
- struct udevice *dev;
-
- ret = uclass_get_device(UCLASS_CLK, 0, &dev);
- if (ret) {
- printf("clk-uclass not found\n");
- return 0;
+ ofnode node;
+ const char *mode;
+ bool matched = false;
+
+ /* find the usb_otg node */
+ node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
+ while (ofnode_valid(node)) {
+ mode = ofnode_read_string(node, "dr_mode");
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = ofnode_by_compatible(node, "snps,dwc2");
}
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ otg_data.regs_otg = ofnode_get_addr(node);
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- struct clk clk;
- ulong rate;
+#ifdef CONFIG_ROCKCHIP_RK3288
+ int ret;
+ u32 phandle, offset;
+ ofnode phy_node;
- clk.id = clks[i].id;
- ret = clk_request(dev, &clk);
- if (ret < 0)
- continue;
+ ret = ofnode_read_u32(node, "phys", &phandle);
+ if (ret)
+ return ret;
- rate = clk_get_rate(&clk);
- printf("%s: %lu\n", clks[i].name, rate);
+ node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(node)) {
+ debug("Not found usb phy device\n");
+ return -ENODEV;
+ }
- clk_free(&clk);
+ phy_node = ofnode_get_parent(node);
+ if (!ofnode_valid(node)) {
+ debug("Not found usb phy device\n");
+ return -ENODEV;
}
+ otg_data.phy_of_node = phy_node;
+ ret = ofnode_read_u32(node, "reg", &offset);
+ if (ret)
+ return ret;
+ otg_data.regs_phy = offset +
+ (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+#endif
+ return dwc2_udc_probe(&otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif /* CONFIG_USB_GADGET_DWC2_OTG */
+
+#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
+#include <dwc3-uboot.h>
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = 0xfe800000,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+ .dis_u2_susphy_quirk = 1,
+ .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif /* CONFIG_USB_DWC3_GADGET */
+
+#endif /* CONFIG_USB_GADGET */
+
+#if CONFIG_IS_ENABLED(FASTBOOT)
+int fastboot_set_reboot_flag(void)
+{
+ printf("Setting reboot to fastboot flag ...\n");
+ /* Set boot mode to fastboot */
+ writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+
return 0;
}
+#endif
-U_BOOT_CMD(
- clock, 2, 1, do_clock,
- "display information about clocks",
- ""
-);
+#ifdef CONFIG_MISC_INIT_R
+__weak int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ ret = rockchip_setup_macaddr();
+
+ return ret;
+}
+#endif
projects / oweals / u-boot.git / blobdiff