Merge git://git.denx.de/u-boot-marvell

[oweals/u-boot.git] / arch / arm / mach-omap2 / omap5 / hw_data.c

diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index a8a6b8a869e539106a5e5234b37f5567f273b41e..bb05e1920b962f8b0e4c2018f67a1d8459f309b7 100644 (file)
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -113,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
        {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 38.4 MHz */
 };
 
+static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
+       {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},              /* 12 MHz   */
+       {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},              /* 20 MHz   */
+       {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},             /* 16.8 MHz */
+       {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},              /* 19.2 MHz */
+       {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},            /* 26 MHz   */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
+       {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},              /* 38.4 MHz */
+};
+
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
        {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
@@ -234,6 +244,17 @@ struct dplls omap5_dplls_es2 = {
        .ddr = NULL
 };
 
+struct dplls dra76x_dplls = {
+       .mpu = mpu_dpll_params_1ghz,
+       .core = core_dpll_params_2128mhz_dra7xx,
+       .per = per_dpll_params_768mhz_dra76x,
+       .abe = abe_dpll_params_sysclk2_361267khz,
+       .iva = iva_dpll_params_2330mhz_dra7xx,
+       .usb = usb_dpll_params_1920mhz,
+       .ddr =  ddr_dpll_params_2664mhz,
+       .gmac = gmac_dpll_params_2000mhz,
+};
+
 struct dplls dra7xx_dplls = {
        .mpu = mpu_dpll_params_1ghz,
        .core = core_dpll_params_2128mhz_dra7xx,
@@ -285,6 +306,22 @@ struct pmic_data tps659038 = {
        .gpio_en = 0,
 };
 
+/* The LP87565*/
+struct pmic_data lp87565 = {
+       .base_offset = LP873X_BUCK_BASE_VOLT_UV,
+       .step = 5000, /* 5 mV represented in uV */
+       /*
+        * Offset codes 0 - 0x13 Invalid.
+        * Offset codes 0x14 0x17 give 10mV steps
+        * Offset codes 0x17 through 0x9D give 5mV steps
+        * So let us start with our operating range from .73V
+        */
+       .start_code = 0x17,
+       .i2c_slave_addr = 0x60,
+       .pmic_bus_init  = gpi2c_init,
+       .pmic_write     = palmas_i2c_write_u8,
+};
+
 /* The LP8732 and LP8733 are software-compatible, use common struct */
 struct pmic_data lp8733 = {
        .base_offset = LP873X_BUCK_BASE_VOLT_UV,
@@ -329,6 +366,15 @@ struct vcores_data omap5430_volts_es2 = {
        .mm.addr = SMPS_REG_ADDR_45_IVA,
        .mm.pmic = &palmas,
        .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
+
+       .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN,
+       .mpu.efuse.reg_bits     = OMAP5_ES2_PROD_REGBITS,
+
+       .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN,
+       .core.efuse.reg_bits    = OMAP5_ES2_PROD_REGBITS,
+
+       .mm.efuse.reg[OPP_NOM]  = OMAP5_ES2_PROD_MM_OPNO_VMIN,
+       .mm.efuse.reg_bits      = OMAP5_ES2_PROD_REGBITS,
 };
 
 /*
@@ -700,6 +746,14 @@ void __weak hw_data_init(void)
        *ctrl = &omap5_ctrl;
        break;
 
+       case DRA762_ABZ_ES1_0:
+       case DRA762_ACD_ES1_0:
+       case DRA762_ES1_0:
+       *prcm = &dra7xx_prcm;
+       *dplls_data = &dra76x_dplls;
+       *ctrl = &dra7xx_ctrl;
+       break;
+
        case DRA752_ES1_0:
        case DRA752_ES1_1:
        case DRA752_ES2_0:
@@ -710,6 +764,7 @@ void __weak hw_data_init(void)
 
        case DRA722_ES1_0:
        case DRA722_ES2_0:
+       case DRA722_ES2_1:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra72x_dplls;
        *ctrl = &dra7xx_ctrl;
@@ -738,12 +793,16 @@ void get_ioregs(const struct ctrl_ioregs **regs)
        case DRA752_ES1_0:
        case DRA752_ES1_1:
        case DRA752_ES2_0:
+       case DRA762_ES1_0:
+       case DRA762_ACD_ES1_0:
+       case DRA762_ABZ_ES1_0:
                *regs = &ioregs_dra7xx_es1;
                break;
        case DRA722_ES1_0:
                *regs = &ioregs_dra72x_es1;
                break;
        case DRA722_ES2_0:
+       case DRA722_ES2_1:
                *regs = &ioregs_dra72x_es2;
                break;