ARM: AM43xx: Add support for RTC only + DDR in self-refresh mode

[oweals/u-boot.git] / arch / arm / mach-omap2 / am33xx / sys_info.c

diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index e4fc461bd81835a0b6518c3c82648533cf3722dc..0181a8cb0cc5c7cf75be63fb59eab55799d5561e 100644 (file)
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -50,16 +50,6 @@ u32 get_cpu_type(void)
        return partnum;
 }
 
-/**
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
-       int mode;
-       mode = readl(&cstat->statusreg) & (DEVICE_MASK);
-       return mode >>= 8;
-}
-
 /**
  * get_sysboot_value(void) - return SYS_BOOT[4:0]
  */
@@ -68,6 +58,24 @@ u32 get_sysboot_value(void)
        return readl(&cstat->statusreg) & SYSBOOT_MASK;
 }
 
+u32 get_sys_clk_index(void)
+{
+       struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+       u32 ind = readl(&ctrl->statusreg);
+
+#ifdef CONFIG_AM43XX
+       u32 src;
+       src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
+       if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
+               return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
+                       CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
+       else /* Value read from SYS BOOT pins */
+#endif
+               return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
+                       CTRL_SYSBOOT_15_14_SHIFT);
+}
+
+
 #ifdef CONFIG_DISPLAY_CPUINFO
 static char *cpu_revs[] = {
                "1.0",
@@ -132,13 +140,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 
        sil_rev = readl(&cdev->deviceid) >> 28;
 
-       if (sil_rev == 1)
-               /* PG 2.0, efuse may not be set. */
-               return MPUPLL_M_800;
-       else if (sil_rev >= 2) {
+       if (sil_rev == 0) {
+               /* No efuse in PG 1.0. Use max speed */
+               return MPUPLL_M_720;
+       } else if (sil_rev >= 1) {
                /* Check what the efuse says our max speed is. */
-               int efuse_arm_mpu_max_freq;
+               int efuse_arm_mpu_max_freq, package_type;
                efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+               package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
+                               PACKAGE_TYPE_SHIFT;
+
+               /* PG 2.0, efuse may not be set. */
+               if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
+                   PACKAGE_TYPE_RESERVED)
+                       return MPUPLL_M_800;
+
                switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
                case AM335X_ZCZ_1000:
                        return MPUPLL_M_1000;
@@ -155,14 +171,30 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
                }
        }
 
-       /* PG 1.0 or otherwise unknown, use the PG1.0 max */
+       /* unknown, use the PG1.0 max */
        return MPUPLL_M_720;
 }
 
+int am335x_get_mpu_vdd(int sil_rev, int frequency)
+{
+       int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
+
+       switch (sel_mask) {
+       case TPS65910_OP_REG_SEL_1_3_2_5:
+               return 1325000;
+       case TPS65910_OP_REG_SEL_1_2_0:
+               return 1200000;
+       case TPS65910_OP_REG_SEL_1_1_0:
+               return 1100000;
+       default:
+               return 1262500;
+       }
+}
+
 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
 {
-       /* For PG2.1 and later, we have one set of values. */
-       if (sil_rev >= 2) {
+       /* For PG2.0 and later, we have one set of values. */
+       if (sil_rev >= 1) {
                switch (frequency) {
                case MPUPLL_M_1000:
                        return TPS65910_OP_REG_SEL_1_3_2_5;
@@ -171,12 +203,13 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
                case MPUPLL_M_720:
                        return TPS65910_OP_REG_SEL_1_2_0;
                case MPUPLL_M_600:
+               case MPUPLL_M_500:
                case MPUPLL_M_300:
-                       return TPS65910_OP_REG_SEL_1_1_3;
+                       return TPS65910_OP_REG_SEL_1_1_0;
                }
        }
 
-       /* Default to PG1.0/PG2.0 values. */
-       return TPS65910_OP_REG_SEL_1_1_3;
+       /* Default to PG1.0 values. */
+       return TPS65910_OP_REG_SEL_1_2_6;
 }
 #endif