return partnum;
}
-/**
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- int mode;
- mode = readl(&cstat->statusreg) & (DEVICE_MASK);
- return mode >>= 8;
-}
-
/**
* get_sysboot_value(void) - return SYS_BOOT[4:0]
*/
return readl(&cstat->statusreg) & SYSBOOT_MASK;
}
+u32 get_sys_clk_index(void)
+{
+ struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+ u32 ind = readl(&ctrl->statusreg);
+
+#ifdef CONFIG_AM43XX
+ u32 src;
+ src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
+ if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
+ return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
+ CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
+ else /* Value read from SYS BOOT pins */
+#endif
+ return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
+ CTRL_SYSBOOT_15_14_SHIFT);
+}
+
+
#ifdef CONFIG_DISPLAY_CPUINFO
static char *cpu_revs[] = {
"1.0",
return MPUPLL_M_720;
}
+int am335x_get_mpu_vdd(int sil_rev, int frequency)
+{
+ int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
+
+ switch (sel_mask) {
+ case TPS65910_OP_REG_SEL_1_3_2_5:
+ return 1325000;
+ case TPS65910_OP_REG_SEL_1_2_0:
+ return 1200000;
+ case TPS65910_OP_REG_SEL_1_1_0:
+ return 1100000;
+ default:
+ return 1262500;
+ }
+}
+
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
{
/* For PG2.0 and later, we have one set of values. */