Merge tag 'u-boot-atmel-fixes-2019.07-a' of git://git.denx.de/u-boot-atmel

[oweals/u-boot.git] / arch / arm / mach-omap2 / am33xx / ddr.c

diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index 6acf30c5db00fe4e363a0fe449e1193cc8306643..3fd1d086ff142473fce73dd46952dc25a42dad40 100644 (file)
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * DDR Configuration for AM33xx devices.
  *
  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm/arch/cpu.h>
@@ -81,6 +80,11 @@ static void configure_mr(int nr, u32 cs)
  */
 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 {
+#ifdef CONFIG_AM43XX
+       struct prm_device_inst *prm_device =
+                       (struct prm_device_inst *)PRM_DEVICE_INST;
+#endif
+
        writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
        writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
        writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
@@ -127,6 +131,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 
+#ifdef CONFIG_AM43XX
+       /*
+        * Disable EMIF_DEVOFF
+        * -> Cold Boot: This is just rewriting the default register value.
+        * -> RTC Resume: Must disable DEVOFF before leveling.
+        */
+       writel(0, &prm_device->emif_ctrl);
+#endif
+
        /* Perform hardware leveling for DDR3 */
        if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
                writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
@@ -139,6 +152,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
                /* Enable read leveling */
                writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 
+               /* Wait 1ms because of L3 timeout error */
+               udelay(1000);
+
                /*
                 * Enable full read and write leveling.  Wait for read and write
                 * leveling bit to clear RDWRLVLFULL_START bit 31
@@ -163,6 +179,14 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  */
 void config_sdram(const struct emif_regs *regs, int nr)
 {
+#ifdef CONFIG_TI816X
+       writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+       writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
+       writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+       writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
+       writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
+       writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+#else
        if (regs->zq_config) {
                writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
                writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
@@ -180,6 +204,11 @@ void config_sdram(const struct emif_regs *regs, int nr)
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
        writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+       /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
+       if (regs->ocp_config)
+               writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
+#endif
 }
 
 /**
@@ -244,8 +273,16 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
         * Enable hardware leveling on the EMIF.  For details about these
         * magic values please see the EMIF registers section of the TRM.
         */
-       writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
-       writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+       if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
+               /* PHY_INVERT_CLKOUT = 1 */
+               writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+               writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+       } else {
+               /* PHY_INVERT_CLKOUT = 0 */
+               writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+               writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+       }
+
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
        writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
@@ -274,8 +311,8 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
-       writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
-       writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+       writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+       writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 
        /*
         * Sequence to ensure that the PHY is again in a known state after