Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / arch / arm / mach-omap2 / am33xx / clock_am33xx.c

diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index 1780bbdb6fb6fa16fb9ec0fef17a447f141f6e99..32cdf63e3dff71bb937b79d3ffe4ad4b50a26167 100644 (file)
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * clock_am33xx.c
  *
  * clocks for AM33XX based boards
  *
  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -52,6 +51,13 @@ const struct dpll_regs dpll_ddr_regs = {
        .cm_div_m2_dpll         = CM_WKUP + 0xA0,
 };
 
+const struct dpll_regs dpll_disp_regs = {
+       .cm_clkmode_dpll        = CM_WKUP + 0x98,
+       .cm_idlest_dpll         = CM_WKUP + 0x48,
+       .cm_clksel_dpll         = CM_WKUP + 0x54,
+       .cm_div_m2_dpll         = CM_WKUP + 0xA4,
+};
+
 struct dpll_params dpll_mpu_opp100 = {
                CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_core_opp100 = {
@@ -109,22 +115,22 @@ const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
 const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
                {505, 15, 2, -1, -1, -1, -1}, /*19.2*/
                {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
-               {303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
-               {303, 12, 2, -1, 4, -1, -1}  /* 26 MHz */
+               {303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
+               {303, 12, 2, -1, -1, -1, -1}  /* 26 MHz */
 };
 
 const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
                {125, 5, 1, -1, -1, -1, -1}, /*19.2*/
                {50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
-               {16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
-               {200, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
+               {16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */
+               {200, 12, 1, -1, -1, -1, -1}  /* 26 MHz */
 };
 
 const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
                {665, 47, 1, -1, -1, -1, -1}, /*19.2*/
                {133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
-               {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
-               {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
+               {266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
+               {133, 12, 1, -1, -1, -1, -1}  /* 26 MHz */
 };
 
 __weak const struct dpll_params *get_dpll_mpu_params(void)