Merge git://git.denx.de/u-boot-usb

[oweals/u-boot.git] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 74a63dd6560b922da6cc98a66df3387f2930536c..f09e7b10e935305a197b9f13640eed16339465ff 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -24,6 +23,11 @@ static struct mbus_win windows[] = {
        /* NOR */
        { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
+
+#ifdef CONFIG_ARMADA_MSYS
+       /* DFX */
+       { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
+#endif
 };
 
 void lowlevel_init(void)
@@ -122,6 +126,14 @@ static const struct sar_freq_modes sar_freq_tab[] = {
        { 0x13,  0x0, 2000, 1000, 933 },
        { 0xff, 0xff,    0,    0,   0 } /* 0xff marks end of array */
 };
+#elif defined(CONFIG_ARMADA_MSYS)
+static const struct sar_freq_modes sar_freq_tab[] = {
+       {  0x0, 0x0,  400,  400, 400 },
+       {  0x2, 0x0,  667,  333, 667 },
+       {  0x3, 0x0,  800,  400, 800 },
+       {  0x5, 0x0,  800,  400, 800 },
+       { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
+};
 #else
 /* SAR frequency values for Armada XP */
 static const struct sar_freq_modes sar_freq_tab[] = {
@@ -145,7 +157,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
        u32 freq;
        int i;
 
-#if defined(CONFIG_ARMADA_375)
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
        val = readl(CONFIG_SAR2_REG);   /* SAR - Sample At Reset */
 #else
        val = readl(CONFIG_SAR_REG);    /* SAR - Sample At Reset */
@@ -161,7 +173,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
 #endif
        for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
                if (sar_freq_tab[i].val == freq) {
-#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
                        *sar_freq = sar_freq_tab[i];
                        return;
 #else
@@ -262,6 +274,23 @@ int print_cpuinfo(void)
                case MV_88F68XX_A0_ID:
                        puts("A0");
                        break;
+               case MV_88F68XX_B0_ID:
+                       puts("B0");
+                       break;
+               default:
+                       printf("?? (%x)", revid);
+                       break;
+               }
+       }
+
+       if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
+               switch (revid) {
+               case 3:
+                       puts("A0");
+                       break;
+               case 4:
+                       puts("A1");
+                       break;
                default:
                        printf("?? (%x)", revid);
                        break;
@@ -281,10 +310,8 @@ int print_cpuinfo(void)
  * and sets the correct windows sizes and base addresses accordingly.
  *
  * These values are set in the scratch registers by the Marvell
- * DDR3 training code, which is executed by the BootROM before the
- * main payload (U-Boot) is executed. This training code is currently
- * only available in the Marvell U-Boot version. It needs to be
- * ported to mainline U-Boot SPL at some point.
+ * DDR3 training code, which is executed by the SPL before the
+ * main payload (U-Boot) is executed.
  */
 static void update_sdram_window_sizes(void)
 {
@@ -472,6 +499,8 @@ u32 mvebu_get_nand_clock(void)
 
        if (mvebu_soc_family() == MVEBU_SOC_A38X)
                reg = MVEBU_DFX_DIV_CLK_CTRL(1);
+       else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
+               reg = MVEBU_DFX_DIV_CLK_CTRL(8);
        else
                reg = MVEBU_CORE_DIV_CLK_CTRL(1);
 
@@ -491,7 +520,7 @@ int arch_misc_init(void)
 }
 #endif /* CONFIG_ARCH_MISC_INIT */
 
-#ifdef CONFIG_MMC_SDHCI_MV
+#if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
 int board_mmc_init(bd_t *bis)
 {
        mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
@@ -501,7 +530,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_SCSI_AHCI_PLAT
 #define AHCI_VENDOR_SPECIFIC_0_ADDR    0xa0
 #define AHCI_VENDOR_SPECIFIC_0_DATA    0xa4
 
@@ -545,15 +573,64 @@ static void ahci_mvebu_regret_option(void __iomem *base)
        writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
 }
 
-void scsi_init(void)
+int board_ahci_enable(void)
 {
-       printf("MVEBU SATA INIT\n");
        ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
        ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
+
+       return 0;
+}
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void scsi_init(void)
+{
+       printf("MVEBU SATA INIT\n");
+       board_ahci_enable();
        ahci_init((void __iomem *)MVEBU_SATA0_BASE);
 }
 #endif
 
+#ifdef CONFIG_USB_XHCI_MVEBU
+#define USB3_MAX_WINDOWS        4
+#define USB3_WIN_CTRL(w)        (0x0 + ((w) * 8))
+#define USB3_WIN_BASE(w)        (0x4 + ((w) * 8))
+
+static void xhci_mvebu_mbus_config(void __iomem *base,
+                       const struct mbus_dram_target_info *dram)
+{
+       int i;
+
+       for (i = 0; i < USB3_MAX_WINDOWS; i++) {
+               writel(0, base + USB3_WIN_CTRL(i));
+               writel(0, base + USB3_WIN_BASE(i));
+       }
+
+       for (i = 0; i < dram->num_cs; i++) {
+               const struct mbus_dram_window *cs = dram->cs + i;
+
+               /* Write size, attributes and target id to control register */
+               writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+                       (dram->mbus_dram_target_id << 4) | 1,
+                       base + USB3_WIN_CTRL(i));
+
+               /* Write base address to base register */
+               writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
+       }
+}
+
+int board_xhci_enable(fdt_addr_t base)
+{
+       const struct mbus_dram_target_info *dram;
+
+       printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
+
+       dram = mvebu_mbus_dram_info();
+       xhci_mvebu_mbus_config((void __iomem *)base, dram);
+
+       return 0;
+}
+#endif
+
 void enable_caches(void)
 {
        /* Avoid problem with e.g. neta ethernet driver */