/*
- * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
- if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID))
+ switch (devid) {
+ case SOC_MV78230_ID:
+ case SOC_MV78260_ID:
+ case SOC_MV78460_ID:
return MVEBU_SOC_AXP;
- if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
- devid == SOC_88F6828_ID)
+ case SOC_88F6720_ID:
+ return MVEBU_SOC_A375;
+
+ case SOC_88F6810_ID:
+ case SOC_88F6820_ID:
+ case SOC_88F6828_ID:
return MVEBU_SOC_A38X;
+ }
return MVEBU_SOC_UNKNOWN;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
+
+#if defined(CONFIG_ARMADA_375)
+/* SAR frequency values for Armada 375 */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0, 0x0, 266, 133, 266 },
+ { 1, 0x0, 333, 167, 167 },
+ { 2, 0x0, 333, 167, 222 },
+ { 3, 0x0, 333, 167, 333 },
+ { 4, 0x0, 400, 200, 200 },
+ { 5, 0x0, 400, 200, 267 },
+ { 6, 0x0, 400, 200, 400 },
+ { 7, 0x0, 500, 250, 250 },
+ { 8, 0x0, 500, 250, 334 },
+ { 9, 0x0, 500, 250, 500 },
+ { 10, 0x0, 533, 267, 267 },
+ { 11, 0x0, 533, 267, 356 },
+ { 12, 0x0, 533, 267, 533 },
+ { 13, 0x0, 600, 300, 300 },
+ { 14, 0x0, 600, 300, 400 },
+ { 15, 0x0, 600, 300, 600 },
+ { 16, 0x0, 666, 333, 333 },
+ { 17, 0x0, 666, 333, 444 },
+ { 18, 0x0, 666, 333, 666 },
+ { 19, 0x0, 800, 400, 267 },
+ { 20, 0x0, 800, 400, 400 },
+ { 21, 0x0, 800, 400, 534 },
+ { 22, 0x0, 900, 450, 300 },
+ { 23, 0x0, 900, 450, 450 },
+ { 24, 0x0, 900, 450, 600 },
+ { 25, 0x0, 1000, 500, 500 },
+ { 26, 0x0, 1000, 500, 667 },
+ { 27, 0x0, 1000, 333, 500 },
+ { 28, 0x0, 400, 400, 400 },
+ { 29, 0x0, 1100, 550, 550 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#elif defined(CONFIG_ARMADA_38X)
+/* SAR frequency values for Armada 38x */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0x0, 0x0, 666, 333, 333 },
+ { 0x2, 0x0, 800, 400, 400 },
+ { 0x4, 0x0, 1066, 533, 533 },
+ { 0x6, 0x0, 1200, 600, 600 },
+ { 0x8, 0x0, 1332, 666, 666 },
+ { 0xc, 0x0, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#else
+/* SAR frequency values for Armada XP */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0xa, 0x5, 800, 400, 400 },
+ { 0x1, 0x5, 1066, 533, 533 },
+ { 0x2, 0x5, 1200, 600, 600 },
+ { 0x2, 0x9, 1200, 600, 400 },
+ { 0x3, 0x5, 1333, 667, 667 },
+ { 0x4, 0x5, 1500, 750, 750 },
+ { 0x4, 0x9, 1500, 750, 500 },
+ { 0xb, 0x9, 1600, 800, 533 },
+ { 0xb, 0xa, 1600, 800, 640 },
+ { 0xb, 0x5, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#endif
+
+void get_sar_freq(struct sar_freq_modes *sar_freq)
+{
+ u32 val;
+ u32 freq;
+ int i;
+
+#if defined(CONFIG_ARMADA_375)
+ val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
+#else
+ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+#endif
+ freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
+#if defined(SAR2_CPU_FREQ_MASK)
+ /*
+ * Shift CPU0 clock frequency select bit from SAR2 register
+ * into correct position
+ */
+ freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
+ >> SAR2_CPU_FREQ_OFFS) << 3;
+#endif
+ for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
+ if (sar_freq_tab[i].val == freq) {
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
+ *sar_freq = sar_freq_tab[i];
+ return;
+#else
+ int k;
+ u8 ffc;
+
+ ffc = (val & SAR_FFC_FREQ_MASK) >>
+ SAR_FFC_FREQ_OFFS;
+ for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
+ if (sar_freq_tab[k].ffc == ffc) {
+ *sar_freq = sar_freq_tab[k];
+ return;
+ }
+ }
+ i = k;
+#endif
+ }
+ }
+
+ /* SAR value not found, return 0 for frequencies */
+ *sar_freq = sar_freq_tab[i - 1];
+}
+
int print_cpuinfo(void)
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+ struct sar_freq_modes sar_freq;
puts("SoC: ");
switch (devid) {
+ case SOC_MV78230_ID:
+ puts("MV78230-");
+ break;
case SOC_MV78260_ID:
puts("MV78260-");
break;
case SOC_MV78460_ID:
puts("MV78460-");
break;
+ case SOC_88F6720_ID:
+ puts("MV88F6720-");
+ break;
case SOC_88F6810_ID:
puts("MV88F6810-");
break;
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
switch (revid) {
case 1:
- puts("A0\n");
+ puts("A0");
break;
case 2:
- puts("B0\n");
+ puts("B0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
+ break;
+ }
+ }
+
+ if (mvebu_soc_family() == MVEBU_SOC_A375) {
+ switch (revid) {
+ case MV_88F67XX_A0_ID:
+ puts("A0");
+ break;
+ default:
+ printf("?? (%x)", revid);
break;
}
}
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
switch (revid) {
case MV_88F68XX_Z1_ID:
- puts("Z1\n");
+ puts("Z1");
break;
case MV_88F68XX_A0_ID:
- puts("A0\n");
+ puts("A0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
break;
}
}
+ get_sar_freq(&sar_freq);
+ printf(" at %d MHz\n", sar_freq.p_clk);
+
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
projects / oweals / u-boot.git / blobdiff