arm: mvebu: Add basic support for the Marvell Armada 375 SoC

[oweals/u-boot.git] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 6ea558c69fd3a31a9c0ad78847f5a2a455a91fb0..9913802a7e754d8be94ed81dcfdfe1f9613db64b 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -49,25 +49,64 @@ int mvebu_soc_family(void)
 {
        u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
 
-       if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID))
+       switch (devid) {
+       case SOC_MV78230_ID:
+       case SOC_MV78260_ID:
+       case SOC_MV78460_ID:
                return MVEBU_SOC_AXP;
 
-       if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
-           devid == SOC_88F6828_ID)
+       case SOC_88F6720_ID:
+               return MVEBU_SOC_A375;
+
+       case SOC_88F6810_ID:
+       case SOC_88F6820_ID:
+       case SOC_88F6828_ID:
                return MVEBU_SOC_A38X;
+       }
 
        return MVEBU_SOC_UNKNOWN;
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
-#if defined(CONFIG_ARMADA_38X)
-/* SAR values for Armada 38x */
-#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18600))
-#define SAR_CPU_FREQ_OFFS      10
-#define SAR_CPU_FREQ_MASK      (0x1f << SAR_CPU_FREQ_OFFS)
-
-struct sar_freq_modes sar_freq_tab[] = {
+#if defined(CONFIG_ARMADA_375)
+/* SAR frequency values for Armada 375 */
+static const struct sar_freq_modes sar_freq_tab[] = {
+       {  0,  0x0,  266,  133,  266 },
+       {  1,  0x0,  333,  167,  167 },
+       {  2,  0x0,  333,  167,  222 },
+       {  3,  0x0,  333,  167,  333 },
+       {  4,  0x0,  400,  200,  200 },
+       {  5,  0x0,  400,  200,  267 },
+       {  6,  0x0,  400,  200,  400 },
+       {  7,  0x0,  500,  250,  250 },
+       {  8,  0x0,  500,  250,  334 },
+       {  9,  0x0,  500,  250,  500 },
+       { 10,  0x0,  533,  267,  267 },
+       { 11,  0x0,  533,  267,  356 },
+       { 12,  0x0,  533,  267,  533 },
+       { 13,  0x0,  600,  300,  300 },
+       { 14,  0x0,  600,  300,  400 },
+       { 15,  0x0,  600,  300,  600 },
+       { 16,  0x0,  666,  333,  333 },
+       { 17,  0x0,  666,  333,  444 },
+       { 18,  0x0,  666,  333,  666 },
+       { 19,  0x0,  800,  400,  267 },
+       { 20,  0x0,  800,  400,  400 },
+       { 21,  0x0,  800,  400,  534 },
+       { 22,  0x0,  900,  450,  300 },
+       { 23,  0x0,  900,  450,  450 },
+       { 24,  0x0,  900,  450,  600 },
+       { 25,  0x0, 1000,  500,  500 },
+       { 26,  0x0, 1000,  500,  667 },
+       { 27,  0x0, 1000,  333,  500 },
+       { 28,  0x0,  400,  400,  400 },
+       { 29,  0x0, 1100,  550,  550 },
+       { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
+};
+#elif defined(CONFIG_ARMADA_38X)
+/* SAR frequency values for Armada 38x */
+static const struct sar_freq_modes sar_freq_tab[] = {
        {  0x0,  0x0,  666, 333, 333 },
        {  0x2,  0x0,  800, 400, 400 },
        {  0x4,  0x0, 1066, 533, 533 },
@@ -77,17 +116,8 @@ struct sar_freq_modes sar_freq_tab[] = {
        { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
 };
 #else
-/* SAR values for Armada XP */
-#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18230))
-#define CONFIG_SAR2_REG                (MVEBU_REGISTER(0x18234))
-#define SAR_CPU_FREQ_OFFS      21
-#define SAR_CPU_FREQ_MASK      (0x7 << SAR_CPU_FREQ_OFFS)
-#define SAR_FFC_FREQ_OFFS      24
-#define SAR_FFC_FREQ_MASK      (0xf << SAR_FFC_FREQ_OFFS)
-#define SAR2_CPU_FREQ_OFFS     20
-#define SAR2_CPU_FREQ_MASK     (0x1 << SAR2_CPU_FREQ_OFFS)
-
-struct sar_freq_modes sar_freq_tab[] = {
+/* SAR frequency values for Armada XP */
+static const struct sar_freq_modes sar_freq_tab[] = {
        {  0xa,  0x5,  800, 400, 400 },
        {  0x1,  0x5, 1066, 533, 533 },
        {  0x2,  0x5, 1200, 600, 600 },
@@ -108,9 +138,13 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
        u32 freq;
        int i;
 
+#if defined(CONFIG_ARMADA_375)
+       val = readl(CONFIG_SAR2_REG);   /* SAR - Sample At Reset */
+#else
        val = readl(CONFIG_SAR_REG);    /* SAR - Sample At Reset */
+#endif
        freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
-#if !defined(CONFIG_ARMADA_38X)
+#if defined(SAR2_CPU_FREQ_MASK)
        /*
         * Shift CPU0 clock frequency select bit from SAR2 register
         * into correct position
@@ -120,7 +154,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
 #endif
        for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
                if (sar_freq_tab[i].val == freq) {
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
                        *sar_freq = sar_freq_tab[i];
                        return;
 #else
@@ -153,12 +187,18 @@ int print_cpuinfo(void)
        puts("SoC:   ");
 
        switch (devid) {
+       case SOC_MV78230_ID:
+               puts("MV78230-");
+               break;
        case SOC_MV78260_ID:
                puts("MV78260-");
                break;
        case SOC_MV78460_ID:
                puts("MV78460-");
                break;
+       case SOC_88F6720_ID:
+               puts("MV88F6720-");
+               break;
        case SOC_88F6810_ID:
                puts("MV88F6810-");
                break;
@@ -187,6 +227,17 @@ int print_cpuinfo(void)
                }
        }
 
+       if (mvebu_soc_family() == MVEBU_SOC_A375) {
+               switch (revid) {
+               case MV_88F67XX_A0_ID:
+                       puts("A0");
+                       break;
+               default:
+                       printf("?? (%x)", revid);
+                       break;
+               }
+       }
+
        if (mvebu_soc_family() == MVEBU_SOC_A38X) {
                switch (revid) {
                case MV_88F68XX_Z1_ID: