Merge git://www.denx.de/git/u-boot-marvell

[oweals/u-boot.git] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index fd66f5939210945800e8b838250118cd1ce9761c..74a63dd6560b922da6cc98a66df3387f2930536c 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -62,6 +62,11 @@ int mvebu_soc_family(void)
        case SOC_88F6820_ID:
        case SOC_88F6828_ID:
                return MVEBU_SOC_A38X;
+
+       case SOC_98DX3236_ID:
+       case SOC_98DX3336_ID:
+       case SOC_98DX4251_ID:
+               return MVEBU_SOC_MSYS;
        }
 
        return MVEBU_SOC_UNKNOWN;
@@ -107,13 +112,15 @@ static const struct sar_freq_modes sar_freq_tab[] = {
 #elif defined(CONFIG_ARMADA_38X)
 /* SAR frequency values for Armada 38x */
 static const struct sar_freq_modes sar_freq_tab[] = {
-       {  0x0,  0x0,  666, 333, 333 },
-       {  0x2,  0x0,  800, 400, 400 },
-       {  0x4,  0x0, 1066, 533, 533 },
-       {  0x6,  0x0, 1200, 600, 600 },
-       {  0x8,  0x0, 1332, 666, 666 },
-       {  0xc,  0x0, 1600, 800, 800 },
-       { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
+       {  0x0,  0x0,  666,  333, 333 },
+       {  0x2,  0x0,  800,  400, 400 },
+       {  0x4,  0x0, 1066,  533, 533 },
+       {  0x6,  0x0, 1200,  600, 600 },
+       {  0x8,  0x0, 1332,  666, 666 },
+       {  0xc,  0x0, 1600,  800, 800 },
+       { 0x10,  0x0, 1866,  933, 933 },
+       { 0x13,  0x0, 2000, 1000, 933 },
+       { 0xff, 0xff,    0,    0,   0 } /* 0xff marks end of array */
 };
 #else
 /* SAR frequency values for Armada XP */
@@ -208,6 +215,15 @@ int print_cpuinfo(void)
        case SOC_88F6828_ID:
                puts("MV88F6828-");
                break;
+       case SOC_98DX3236_ID:
+               puts("98DX3236-");
+               break;
+       case SOC_98DX3336_ID:
+               puts("98DX3336-");
+               break;
+       case SOC_98DX4251_ID:
+               puts("98DX4251-");
+               break;
        default:
                puts("Unknown-");
                break;
@@ -452,8 +468,15 @@ int arch_cpu_init(void)
 
 u32 mvebu_get_nand_clock(void)
 {
+       u32 reg;
+
+       if (mvebu_soc_family() == MVEBU_SOC_A38X)
+               reg = MVEBU_DFX_DIV_CLK_CTRL(1);
+       else
+               reg = MVEBU_CORE_DIV_CLK_CTRL(1);
+
        return CONFIG_SYS_MVEBU_PLL_CLOCK /
-               ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
+               ((readl(reg) &
                  NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
 }
 
@@ -468,7 +491,7 @@ int arch_misc_init(void)
 }
 #endif /* CONFIG_ARCH_MISC_INIT */
 
-#ifdef CONFIG_MV_SDHCI
+#ifdef CONFIG_MMC_SDHCI_MV
 int board_mmc_init(bd_t *bis)
 {
        mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,