arm64: mvebu: Add basic support for the Marvell Armada 7K/8K SoC

[oweals/u-boot.git] / arch / arm / mach-mvebu / armada8k / cpu.c

diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
new file mode 100644 (file)
index 0000000..036430c
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Armada 7k/8k */
+#define MVEBU_RFU_BASE                 (MVEBU_REGISTER(0x6f0000))
+#define RFU_GLOBAL_SW_RST              (MVEBU_RFU_BASE + 0x84)
+#define RFU_SW_RESET_OFFSET            0
+
+static struct mm_region mvebu_mem_map[] = {
+       {
+               /* RAM */
+               .phys = 0x0UL,
+               .virt = 0x0UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       },
+       {
+               /* SRAM, MMIO regions - AP806 region */
+               .phys = 0xf0000000UL,
+               .virt = 0xf0000000UL,
+               .size = 0x01000000UL,   /* 16MiB internal registers */
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE
+       },
+       {
+               /* SRAM, MMIO regions - CP110 region */
+               .phys = 0xf2000000UL,
+               .virt = 0xf2000000UL,
+               .size = 0x02000000UL,   /* 32MiB internal registers */
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE
+       },
+       {
+               /* List terminator */
+               0,
+       }
+};
+
+struct mm_region *mem_map = mvebu_mem_map;
+
+void reset_cpu(ulong ignored)
+{
+       u32 reg;
+
+       reg = readl(RFU_GLOBAL_SW_RST);
+       reg &= ~(1 << RFU_SW_RESET_OFFSET);
+       writel(reg, RFU_GLOBAL_SW_RST);
+}