USB: DM: Convert i.MX5 ehci code to driver model

[oweals/u-boot.git] / arch / arm / mach-kirkwood / cpu.c

diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c
index d54de53f31dc049c785bd3ca7c043aa790f02f56..8f8e3003854c213d7b04c2e974058230f90b605b 100644 (file)
--- a/arch/arm/mach-kirkwood/cpu.c
+++ b/arch/arm/mach-kirkwood/cpu.c
@@ -46,69 +46,31 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval)
        return (0x0000ffff & j);
 }
 
-/*
- * kw_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Kirkwood Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int kw_config_adr_windows(void)
-{
-       struct kwwin_registers *winregs =
-               (struct kwwin_registers *)KW_CPU_WIN_BASE;
-
+static struct mbus_win windows[] = {
        /* Window 0: PCIE MEM address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
-               KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
-
-       writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
-       writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
-       writel(0x0, &winregs[0].remap_hi);
+       { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
+         KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
 
        /* Window 1: PCIE IO address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
-               KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
-       writel(KW_DEFADR_PCI_IO, &winregs[1].base);
-       writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
-       writel(0x0, &winregs[1].remap_hi);
+       { KW_DEFADR_PCI_IO, 1024 * 64,
+         KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
 
        /* Window 2: NAND Flash address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-               KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
-       writel(KW_DEFADR_NANDF, &winregs[2].base);
-       writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
-       writel(0x0, &winregs[2].remap_hi);
+       { KW_DEFADR_NANDF, 1024 * 1024 * 128,
+         KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
 
        /* Window 3: SPI Flash address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-               KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
-       writel(KW_DEFADR_SPIF, &winregs[3].base);
-       writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
-       writel(0x0, &winregs[3].remap_hi);
+       { KW_DEFADR_SPIF, 1024 * 1024 * 128,
+         KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
 
        /* Window 4: BOOT Memory address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-               KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
-       writel(KW_DEFADR_BOOTROM, &winregs[4].base);
+       { KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
+         KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
 
        /* Window 5: Security SRAM address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
-               KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
-       writel(KW_DEFADR_SASRAM, &winregs[5].base);
-
-       /* Window 6-7: Disabled */
-       writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
-       writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
-
-       return 0;
-}
+       { KW_DEFADR_SASRAM, 1024 * 64,
+         KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
+};
 
 /*
  * SYSRSTn Duration Counter Support
@@ -221,15 +183,13 @@ int arch_cpu_init(void)
        struct kwcpu_registers *cpureg =
                (struct kwcpu_registers *)KW_CPU_REG_BASE;
 
-       /* Linux expects` the internal registers to be at 0xf1000000 */
+       /* Linux expects the internal registers to be at 0xf1000000 */
        writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
 
        /* Enable and invalidate L2 cache in write through mode */
        writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
        invalidate_l2_cache();
 
-       kw_config_adr_windows();
-
 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
        /*
         * Configures the I/O voltage of the pads connected to Egigabit
@@ -291,11 +251,13 @@ int arch_misc_init(void)
        temp |= (1 << 22);
        writefr_extra_feature_reg(temp);
 
-       icache_enable();
        /* Change reset vector to address 0x0 */
        temp = get_cr();
        set_cr(temp & ~CR_V);
 
+       /* Configure mbus windows */
+       mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
+
        /* checks and execute resset to factory event */
        kw_sysrst_check();