#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
/* NETCP pktdma */
+#ifdef CONFIG_SOC_K2G
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE 113
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE 114
+#else
#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
+#endif
/* Chip Interrupt Controller */
#define KS2_CIC2_BASE 0x02608000
#define KS2_LPSC_GEM_0 15
#define KS2_LPSC_TETRIS 52
#define KS2_TETRIS_PWR_DOMAIN 31
+#define KS2_GEM_0_PWR_DOMAIN 8
/* Chip configuration unlock codes and registers */
#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)