ARM: k2g: add a workaround to reset the phy
[oweals/u-boot.git] / arch / arm / mach-keystone / include / mach / hardware-k2g.h
index ca2a119d390139e4750358f874b3d35422f3a21e..971c081bb3c3b9303ae05ab3fcacf1162280366f 100644 (file)
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * K2G: SoC definitions
  *
  * (C) Copyright 2015
  *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #ifndef __ASM_ARCH_HARDWARE_K2G_H
 
 #define K2G_GPIO0_BASE                 0X02603000
 #define K2G_GPIO1_BASE                 0X0260a000
+#define K2G_GPIO0_BANK0_BASE           K2G_GPIO0_BASE + 0x10
 #define K2G_GPIO1_BANK2_BASE           K2G_GPIO1_BASE + 0x38
 #define K2G_GPIO_DIR_OFFSET            0x0
+#define K2G_GPIO_OUTDATA_OFFSET                0x4
 #define K2G_GPIO_SETDATA_OFFSET                0x8
+#define K2G_GPIO_CLRDATA_OFFSET                0xC
+
+/* BOOTCFG RESETMUX8 */
+#define KS2_RSTMUX8                    (KS2_DEVICE_STATE_CTRL_BASE + 0x328)
+
+/* RESETMUX register definitions */
+#define RSTMUX_LOCK8_SHIFT             0x0
+#define RSTMUX_LOCK8_MASK              (0x1 << 0)
+#define RSTMUX_OMODE8_SHIFT            0x1
+#define RSTMUX_OMODE8_MASK             (0x7 << 1)
+#define RSTMUX_OMODE8_DEV_RESET                0x2
+#define RSTMUX_OMODE8_INT              0x3
+#define RSTMUX_OMODE8_INT_AND_DEV_RESET        0x4
+
+/* DEVSTAT register definition */
+#define KS2_DEVSTAT_REFCLK_SHIFT        7
+#define KS2_DEVSTAT_REFCLK_MASK                (0x7 << 7)
 
+/* GPMC */
+#define KS2_GPMC_BASE                  0x21818000
+
+/* SYSCLK indexes */
+#define SYSCLK_19MHz   0
+#define SYSCLK_24MHz   1
+#define SYSCLK_25MHz   2
+#define SYSCLK_26MHz   3
+#define MAX_SYSCLK     4
+
+#ifndef __ASSEMBLY__
+static inline u8 get_sysclk_index(void)
+{
+       u32 dev_stat = __raw_readl(KS2_DEVSTAT);
+       return (dev_stat & KS2_DEVSTAT_REFCLK_MASK) >> KS2_DEVSTAT_REFCLK_SHIFT;
+}
+#endif
 #endif /* __ASM_ARCH_HARDWARE_K2G_H */