arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded data

[oweals/u-boot.git] / arch / arm / mach-keystone / include / mach / clock-k2l.h

diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index 485746dea28af4cce88942d5d8e023d1f6121dbb..dec19396d612b76c56a08de32a43880bd01b3ef3 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -10,28 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2L_H
 #define __ASM_ARCH_CLOCK_K2L_H
 
-#define CLK_LIST(CLK)\
-       CLK(0, core_pll_clk)\
-       CLK(1, pass_pll_clk)\
-       CLK(2, tetris_pll_clk)\
-       CLK(3, ddr3_pll_clk)\
-       CLK(4, sys_clk0_clk)\
-       CLK(5, sys_clk0_1_clk)\
-       CLK(6, sys_clk0_2_clk)\
-       CLK(7, sys_clk0_3_clk)\
-       CLK(8, sys_clk0_4_clk)\
-       CLK(9, sys_clk0_6_clk)\
-       CLK(10, sys_clk0_8_clk)\
-       CLK(11, sys_clk0_12_clk)\
-       CLK(12, sys_clk0_24_clk)\
-       CLK(13, sys_clk1_clk)\
-       CLK(14, sys_clk1_3_clk)\
-       CLK(15, sys_clk1_4_clk)\
-       CLK(16, sys_clk1_6_clk)\
-       CLK(17, sys_clk1_12_clk)\
-       CLK(18, sys_clk2_clk)\
-       CLK(19, sys_clk3_clk)\
-
 #define PLLSET_CMD_LIST        "<pa|arm|ddr3>"
 
 #define KS2_CLK1_6     sys_clk0_6_clk
@@ -62,7 +40,7 @@
 
 /* k2l DEV supports 800, 1000, 1200 MHz */
 #define DEV_SUPPORTED_SPEEDS   0x383
-/* k2l ARM supportd 800, 1000, 1200, MHz */
-#define ARM_SUPPORTED_SPEEDS   0x383
+/* k2l ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
+#define ARM_SUPPORTED_SPEEDS   0x3ef
 
 #endif