__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
- __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
+ if (!cpu_is_k2g())
+ __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
+ if (cpu_is_k2g()) {
+ setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+ }
+
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
puts("\nClear entire DDR3 memory to enable ECC\n");
/* save the SES MPAX regs */
- msmc_get_ses_mpax(8, 0, mpax);
+ if (cpu_is_k2g())
+ msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+ else
+ msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
/* setup edma slot 1 configuration */
slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
access slave interface so that edma driver can access */
- msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
- KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+ if (cpu_is_k2g()) {
+ msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
+ base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg,
+ MPAX_SEG_2G);
+ } else {
+ msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
+ base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg,
+ MPAX_SEG_2G);
+ }
if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
edma_blks = KS2_MSMC_MAP_SEG_NUM <<
qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
/* restore the SES MPAX regs */
- msmc_set_ses_mpax(8, 0, mpax);
+ if (cpu_is_k2g())
+ msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+ else
+ msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
}
static void ddr3_ecc_init_range(u32 base)