ARM: dts: rmobile: Reserve space in R-Car Gen3 DTs

[oweals/u-boot.git] / arch / arm / mach-keystone / ddr3.c

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index ee8e12e878eb860da4e3cd8efa289d99e20a6d77..7dea600d509b9cc712f9be510659da166df3c443 100644 (file)
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Keystone2: DDR3 initialization
  *
  * (C) Copyright 2012-2014
  *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
+#include <cpu_func.h>
+#include <env.h>
 #include <asm/io.h>
 #include <common.h>
 #include <asm/arch/msmc.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/psc_defs.h>
+#include <linux/delay.h>
 
 #include <asm/ti-common/ti-edma3.h>
 
@@ -52,8 +54,7 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
        __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
        __raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
        __raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
-       if (!cpu_is_k2g())
-               __raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
+       __raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
        __raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
        __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
 
@@ -66,11 +67,33 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
                ;
 
        if (cpu_is_k2g()) {
-               setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
+                               phy_cfg->datx8_2_mask,
+                               phy_cfg->datx8_2_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
+                               phy_cfg->datx8_3_mask,
+                               phy_cfg->datx8_3_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
+                               phy_cfg->datx8_4_mask,
+                               phy_cfg->datx8_4_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
+                               phy_cfg->datx8_5_mask,
+                               phy_cfg->datx8_5_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
+                               phy_cfg->datx8_6_mask,
+                               phy_cfg->datx8_6_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
+                               phy_cfg->datx8_7_mask,
+                               phy_cfg->datx8_7_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
+                               phy_cfg->datx8_8_mask,
+                               phy_cfg->datx8_8_val);
        }
 
        __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
@@ -310,7 +333,7 @@ void ddr3_check_ecc_int(u32 base)
        int ecc_test = 0;
        u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
 
-       env = getenv("ecc_test");
+       env = env_get("ecc_test");
        if (env)
                ecc_test = simple_strtol(env, NULL, 0);