ARM: dts: rmobile: Reserve space in R-Car Gen3 DTs

[oweals/u-boot.git] / arch / arm / mach-keystone / ddr3.c

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index dfb27b5ba20f5b0709be3ba398f228892c0aff33..7dea600d509b9cc712f9be510659da166df3c443 100644 (file)
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Keystone2: DDR3 initialization
  *
  * (C) Copyright 2012-2014
  *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
+#include <cpu_func.h>
+#include <env.h>
 #include <asm/io.h>
 #include <common.h>
 #include <asm/arch/msmc.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/psc_defs.h>
+#include <linux/delay.h>
 
 #include <asm/ti-common/ti-edma3.h>
 
@@ -64,6 +66,36 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
        while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
                ;
 
+       if (cpu_is_k2g()) {
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
+                               phy_cfg->datx8_2_mask,
+                               phy_cfg->datx8_2_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
+                               phy_cfg->datx8_3_mask,
+                               phy_cfg->datx8_3_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
+                               phy_cfg->datx8_4_mask,
+                               phy_cfg->datx8_4_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
+                               phy_cfg->datx8_5_mask,
+                               phy_cfg->datx8_5_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
+                               phy_cfg->datx8_6_mask,
+                               phy_cfg->datx8_6_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
+                               phy_cfg->datx8_7_mask,
+                               phy_cfg->datx8_7_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
+                               phy_cfg->datx8_8_mask,
+                               phy_cfg->datx8_8_val);
+       }
+
        __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
        while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
                ;
@@ -129,7 +161,10 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size)
        puts("\nClear entire DDR3 memory to enable ECC\n");
 
        /* save the SES MPAX regs */
-       msmc_get_ses_mpax(8, 0, mpax);
+       if (cpu_is_k2g())
+               msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+       else
+               msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
 
        /* setup edma slot 1 configuration */
        slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
@@ -160,8 +195,17 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size)
        for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
                /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
                   access slave interface so that edma driver can access */
-               msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
-                                    KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+               if (cpu_is_k2g()) {
+                       msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
+                                            base >> KS2_MSMC_SEG_SIZE_SHIFT,
+                                            KS2_MSMC_DST_SEG_BASE + seg,
+                                            MPAX_SEG_2G);
+               } else {
+                       msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
+                                            base >> KS2_MSMC_SEG_SIZE_SHIFT,
+                                            KS2_MSMC_DST_SEG_BASE + seg,
+                                            MPAX_SEG_2G);
+               }
 
                if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
                        edma_blks = KS2_MSMC_MAP_SEG_NUM <<
@@ -188,7 +232,10 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size)
        qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
 
        /* restore the SES MPAX regs */
-       msmc_set_ses_mpax(8, 0, mpax);
+       if (cpu_is_k2g())
+               msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+       else
+               msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
 }
 
 static void ddr3_ecc_init_range(u32 base)
@@ -286,7 +333,7 @@ void ddr3_check_ecc_int(u32 base)
        int ecc_test = 0;
        u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
 
-       env = getenv("ecc_test");
+       env = env_get("ecc_test");
        if (env)
                ecc_test = simple_strtol(env, NULL, 0);