#include <common.h>
#include <cpu_func.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
#include <spl.h>
#include "common.h"
#include <dm.h>
#include <remoteproc.h>
+#include <asm/cache.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <fdt_support.h>
#include <asm/arch/sys_proto.h>
u32 soc, rev;
char *name;
- soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
- DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
+ soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
+ JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
printf("SoC: ");
switch (soc) {
- case AM654:
- name = "AM654";
+ case AM65X:
+ name = "AM65x";
break;
case J721E:
name = "J721E";
}
}
}
+
+void spl_enable_dcache(void)
+{
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+ phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+
+ dram_init_banksize();
+
+ /* reserve TLB table */
+ gd->arch.tlb_size = PGTABLE_SIZE;
+
+ ram_top += get_effective_memsize();
+ /* keep ram_top in the 32-bit address space */
+ if (ram_top >= 0x100000000)
+ ram_top = (phys_addr_t) 0x100000000;
+
+ gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+ debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+
+ dcache_enable();
+#endif
+}
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+void spl_board_prepare_for_boot(void)
+{
+ dcache_disable();
+}
+
+void spl_board_prepare_for_boot_linux(void)
+{
+ dcache_disable();
+}
+#endif