Merge tag 'mips-fixes-for-2020.04' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / arch / arm / mach-imx / mx7 / soc.c

diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 3f74f8a3ede339b575337d930750e289a8e2e949..4aafeed188101a6d6f90bc5450a985fba3ff6d8f 100644 (file)
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -14,6 +14,7 @@
 #include <asm/arch/imx-rdc.h>
 #include <asm/arch/crm_regs.h>
 #include <dm.h>
+#include <env.h>
 #include <imx_thermal.h>
 #include <fsl_sec.h>
 #include <asm/setup.h>
@@ -121,7 +122,7 @@ static void isolate_resource(void)
 }
 #endif
 
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_IMX_HAB)
 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
        .bank = 1,
        .word = 3,
@@ -164,15 +165,6 @@ u32 __weak get_board_rev(void)
 }
 #endif
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-/* enable all periherial can be accessed in nosec mode */
-static void init_csu(void)
-{
-       int i = 0;
-       for (i = 0; i < CSU_NUM_REGS; i++)
-               writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
-}
-
 static void imx_enet_mdio_fixup(void)
 {
        struct iomuxc_gpr_base_regs *gpr_regs =
@@ -191,6 +183,54 @@ static void imx_enet_mdio_fixup(void)
        }
 }
 
+static void init_cpu_basic(void)
+{
+       imx_enet_mdio_fixup();
+
+#ifdef CONFIG_APBH_DMA
+       /* Start APBH DMA */
+       mxs_dma_init();
+#endif
+}
+
+#ifdef CONFIG_IMX_BOOTAUX
+/*
+ * Table of mappings of physical mem regions in both
+ * Cortex-A7 and Cortex-M4 address spaces.
+ *
+ * For additional details check sections 2.1.2 and 2.1.3 in
+ * i.MX7Dual Applications Processor Reference Manual
+ *
+ */
+const struct rproc_att hostmap[] = {
+       /* aux core , host core,  size */
+       { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
+       { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
+       { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
+       { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
+       { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
+       { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
+       { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
+       { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
+       { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
+       { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
+       { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
+       { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
+       { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */
+       { /* sentinel */ }
+};
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/* enable all periherial can be accessed in nosec mode */
+static void init_csu(void)
+{
+       int i = 0;
+
+       for (i = 0; i < CSU_NUM_REGS; i++)
+               writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
+}
+
 static void imx_gpcv2_init(void)
 {
        u32 val, i;
@@ -269,12 +309,7 @@ int arch_cpu_init(void)
        /* Disable PDE bit of WMCR register */
        imx_wdog_disable_powerdown();
 
-       imx_enet_mdio_fixup();
-
-#ifdef CONFIG_APBH_DMA
-       /* Start APBH DMA */
-       mxs_dma_init();
-#endif
+       init_cpu_basic();
 
 #if CONFIG_IS_ENABLED(IMX_RDC)
        isolate_resource();
@@ -286,6 +321,13 @@ int arch_cpu_init(void)
 
        return 0;
 }
+#else
+int arch_cpu_init(void)
+{
+       init_cpu_basic();
+
+       return 0;
+}
 #endif
 
 #ifdef CONFIG_ARCH_MISC_INIT
@@ -368,8 +410,10 @@ void s_init(void)
 
 void reset_misc(void)
 {
-#ifdef CONFIG_VIDEO_MXS
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
        lcdif_power_down();
 #endif
+#endif
 }